[PATCH] D43374: [ARM]Decoding MSR with unpredictable destination register causes an assert

[Simi Pallipurath via Phabricator via llvm-commits]

simpal01 created this revision.
simpal01 added reviewers: resistor, olista01.
Herald added subscribers: llvm-commits, kristof.beyls, javed.absar.

This patch handling:

1. Enable parsing of raw encodings of system registers .
2. Allows UNPREDICTABLE sysregs to be decoded to a raw number in the same way that disasslib does, rather than llvm crashing.
3. Disassemble msr/mrs with unpredictable sysregs as SoftFail.
  1. Fix regression due to SoftFailing some encodings.

Patch by Chris Ryder

      
  
     


Repository:
  rL LLVM

https://reviews.llvm.org/D43374

Files:
  lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  lib/Target/ARM/Disassembler/ARMDisassembler.cpp
  lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
  test/MC/ARM/thumbv8m.s
  test/MC/Disassembler/ARM/invalid-thumb-MSR-MClass.txt

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