[llvm] r320503 - [MachineOperand][MIR] Add isRenamable to MachineOperand.
Mikael Holmén via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 15 23:22:51 PST 2018
Hi Geoff,
I've got a question about the new verifier check added in this patch.
On 12/12/2017 06:53 PM, Geoff Berry via llvm-commits wrote:
[...]
> Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=320503&r1=320502&r2=320503&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
> +++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Tue Dec 12 09:53:59 2017
> @@ -1101,6 +1101,14 @@ MachineVerifier::visitMachineOperand(con
> }
> }
> }
> + if (MO->isRenamable() &&
> + ((MO->isDef() && MI->hasExtraDefRegAllocReq()) ||
> + (MO->isUse() && MI->hasExtraSrcRegAllocReq()))) {
> + report("Illegal isRenamable setting for opcode with extra regalloc "
> + "requirements",
> + MO, MONum);
> + return;
> + }
Is this really doing what we want?
hasExtraDefRegAllocReq() takes a default argument that currently is
"AnyInBundle":
bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const
This means that it complains on the following bundle:
BUNDLE implicit-def $a1, implicit-def renamable $a0 {
$a1 = sub undef $a1, undef $a1
renamable $a0 = mv_nimm32 124
}
*** Bad machine code: Illegal isRenamable setting for opcode with extra
regalloc requirements ***
- function: main
- basic block: %bb.0 (0x4ce2b78)
- instruction: BUNDLE implicit-def $a1, implicit-def renamable $a0
- operand 2: implicit-def renamable $a0
LLVM ERROR: Found 1 machine code errors.
So $a0 is defined by mv_nimm32 and $a0 is renamable since the mv_nimm32
instruction does not have the hasExtraDefRegAllocReq property set. The
implicit-def of $a0 in the BUNDLE instruction is also renamable.
Then we have the sub instruction which defines $a1. $a1 is not renamable
since the sub instruction has hasExtraDefRegAllocReq = 1. The
implicit-def of $a1 in the BUNDLE doesn't have renamable either.
This bundle looks correct to me but the verifier complains on it and
says that $a0 in the BUNDLE must not be renamable, and that is because
there exist _any_ instruction inside the bundle that has
hasExtraDefRegAllocReq = 1. But that instruction isn't even defining $a0
so I think it's incorrect.
Isn't this unnecessarily harsh?
Regards,
Mikael
> } else {
> // Virtual register.
> const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
>
> Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=320503&r1=320502&r2=320503&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original)
> +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Tue Dec 12 09:53:59 2017
> @@ -699,11 +699,13 @@ bool RegAllocFast::setPhysReg(MachineIns
> bool Dead = MO.isDead();
> if (!MO.getSubReg()) {
> MO.setReg(PhysReg);
> + MO.setIsRenamableIfNoExtraRegAllocReq();
> return MO.isKill() || Dead;
> }
>
> // Handle subregister index.
> MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
> + MO.setIsRenamableIfNoExtraRegAllocReq();
> MO.setSubReg(0);
>
> // A kill flag implies killing the full register. Add corresponding super
>
> Modified: llvm/trunk/lib/CodeGen/VirtRegMap.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegMap.cpp?rev=320503&r1=320502&r2=320503&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/VirtRegMap.cpp (original)
> +++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp Tue Dec 12 09:53:59 2017
> @@ -530,6 +530,7 @@ void VirtRegRewriter::rewrite() {
> // Rewrite. Note we could have used MachineOperand::substPhysReg(), but
> // we need the inlining here.
> MO.setReg(PhysReg);
> + MO.setIsRenamableIfNoExtraRegAllocReq();
> }
>
> // Add any missing super-register kills after rewriting the whole
>
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=320503&r1=320502&r2=320503&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Dec 12 09:53:59 2017
> @@ -1357,25 +1357,34 @@ void ARMBaseInstrInfo::expandMEMCPY(Mach
>
> MachineInstrBuilder LDM, STM;
> if (isThumb1 || !MI->getOperand(1).isDead()) {
> + MachineOperand LDWb(MI->getOperand(1));
> + LDWb.setIsRenamable(false);
> LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD
> : isThumb1 ? ARM::tLDMIA_UPD
> : ARM::LDMIA_UPD))
> - .add(MI->getOperand(1));
> + .add(LDWb);
> } else {
> LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA : ARM::LDMIA));
> }
>
> if (isThumb1 || !MI->getOperand(0).isDead()) {
> + MachineOperand STWb(MI->getOperand(0));
> + STWb.setIsRenamable(false);
> STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD
> : isThumb1 ? ARM::tSTMIA_UPD
> : ARM::STMIA_UPD))
> - .add(MI->getOperand(0));
> + .add(STWb);
> } else {
> STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA));
> }
>
> - LDM.add(MI->getOperand(3)).add(predOps(ARMCC::AL));
> - STM.add(MI->getOperand(2)).add(predOps(ARMCC::AL));
> + MachineOperand LDBase(MI->getOperand(3));
> + LDBase.setIsRenamable(false);
> + LDM.add(LDBase).add(predOps(ARMCC::AL));
> +
> + MachineOperand STBase(MI->getOperand(2));
> + STBase.setIsRenamable(false);
> + STM.add(STBase).add(predOps(ARMCC::AL));
>
> // Sort the scratch registers into ascending order.
> const TargetRegisterInfo &TRI = getRegisterInfo();
>
> Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=320503&r1=320502&r2=320503&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Tue Dec 12 09:53:59 2017
> @@ -606,8 +606,11 @@ void ARMExpandPseudo::ExpandVTBL(Machine
>
> // Transfer the destination register operand.
> MIB.add(MI.getOperand(OpIdx++));
> - if (IsExt)
> - MIB.add(MI.getOperand(OpIdx++));
> + if (IsExt) {
> + MachineOperand VdSrc(MI.getOperand(OpIdx++));
> + VdSrc.setIsRenamable(false);
> + MIB.add(VdSrc);
> + }
>
> bool SrcIsKill = MI.getOperand(OpIdx).isKill();
> unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
> @@ -616,7 +619,9 @@ void ARMExpandPseudo::ExpandVTBL(Machine
> MIB.addReg(D0);
>
> // Copy the other source register operand.
> - MIB.add(MI.getOperand(OpIdx++));
> + MachineOperand VmSrc(MI.getOperand(OpIdx++));
> + VmSrc.setIsRenamable(false);
> + MIB.add(VmSrc);
>
> // Copy the predicate operands.
> MIB.add(MI.getOperand(OpIdx++));
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=320503&r1=320502&r2=320503&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Dec 12 09:53:59 2017
> @@ -8974,8 +8974,11 @@ ARMTargetLowering::EmitInstrWithCustomIn
>
> // Thumb1 post-indexed loads are really just single-register LDMs.
> case ARM::tLDR_postidx: {
> + MachineOperand Def(MI.getOperand(1));
> + if (TargetRegisterInfo::isPhysicalRegister(Def.getReg()))
> + Def.setIsRenamable(false);
> BuildMI(*BB, MI, dl, TII->get(ARM::tLDMIA_UPD))
> - .add(MI.getOperand(1)) // Rn_wb
> + .add(Def) // Rn_wb
> .add(MI.getOperand(2)) // Rn
> .add(MI.getOperand(3)) // PredImm
> .add(MI.getOperand(4)) // PredReg
>
> Modified: llvm/trunk/test/CodeGen/AArch64/arm64-misched-multimmo.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-misched-multimmo.ll?rev=320503&r1=320502&r2=320503&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/arm64-misched-multimmo.ll (original)
> +++ llvm/trunk/test/CodeGen/AArch64/arm64-misched-multimmo.ll Tue Dec 12 09:53:59 2017
> @@ -8,11 +8,11 @@
> ; Check that no scheduling dependencies are created between the paired loads and the store during post-RA MI scheduling.
> ;
> ; CHECK-LABEL: # Machine code for function foo:
> -; CHECK: SU(2): %w{{[0-9]+}}, %w{{[0-9]+}} = LDPWi
> +; CHECK: SU(2): renamable %w{{[0-9]+}}, renamable %w{{[0-9]+}} = LDPWi
> ; CHECK: Successors:
> ; CHECK-NOT: ch SU(4)
> ; CHECK: SU(3)
> -; CHECK: SU(4): STRWui %wzr, %x{{[0-9]+}}
> +; CHECK: SU(4): STRWui %wzr, renamable %x{{[0-9]+}}
> define i32 @foo() {
> entry:
> %0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G2, i64 0, i64 0), align 4
>
> Modified: llvm/trunk/test/CodeGen/AMDGPU/shrink-carry.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/shrink-carry.mir?rev=320503&r1=320502&r2=320503&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AMDGPU/shrink-carry.mir (original)
> +++ llvm/trunk/test/CodeGen/AMDGPU/shrink-carry.mir Tue Dec 12 09:53:59 2017
> @@ -1,7 +1,7 @@
> # RUN: llc -march=amdgcn -verify-machineinstrs -start-before si-shrink-instructions -stop-before si-insert-skips -o - %s | FileCheck -check-prefix=GCN %s
>
> # GCN-LABEL: name: subbrev{{$}}
> -# GCN: V_SUBBREV_U32_e64 0, undef %vgpr0, killed %vcc, implicit %exec
> +# GCN: V_SUBBREV_U32_e64 0, undef %vgpr0, killed renamable %vcc, implicit %exec
>
> ---
> name: subbrev
> @@ -25,7 +25,7 @@ body: |
> ...
>
> # GCN-LABEL: name: subb{{$}}
> -# GCN: V_SUBB_U32_e64 undef %vgpr0, 0, killed %vcc, implicit %exec
> +# GCN: V_SUBB_U32_e64 undef %vgpr0, 0, killed renamable %vcc, implicit %exec
>
> ---
> name: subb
> @@ -49,7 +49,7 @@ body: |
> ...
>
> # GCN-LABEL: name: addc{{$}}
> -# GCN: V_ADDC_U32_e32 0, undef %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec
> +# GCN: V_ADDC_U32_e32 0, undef renamable %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec
>
> ---
> name: addc
> @@ -73,7 +73,7 @@ body: |
> ...
>
> # GCN-LABEL: name: addc2{{$}}
> -# GCN: V_ADDC_U32_e32 0, undef %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec
> +# GCN: V_ADDC_U32_e32 0, undef renamable %vgpr0, implicit-def %vcc, implicit killed %vcc, implicit %exec
>
> ---
> name: addc2
>
> Modified: llvm/trunk/test/CodeGen/AMDGPU/splitkit.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/splitkit.mir?rev=320503&r1=320502&r2=320503&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AMDGPU/splitkit.mir (original)
> +++ llvm/trunk/test/CodeGen/AMDGPU/splitkit.mir Tue Dec 12 09:53:59 2017
> @@ -37,13 +37,13 @@ body: |
> # CHECK: [[REG0:%sgpr[0-9]+]] = COPY %sgpr0
> # CHECK: [[REG1:%sgpr[0-9]+]] = COPY %sgpr2
> # CHECK: S_NOP 0
> -# CHECK: S_NOP 0, implicit [[REG0]]
> -# CHECK: S_NOP 0, implicit [[REG1]]
> -# CHECK: %sgpr0 = COPY [[REG0]]
> -# CHECK: %sgpr2 = COPY [[REG1]]
> +# CHECK: S_NOP 0, implicit renamable [[REG0]]
> +# CHECK: S_NOP 0, implicit renamable [[REG1]]
> +# CHECK: %sgpr0 = COPY renamable [[REG0]]
> +# CHECK: %sgpr2 = COPY renamable [[REG1]]
> # CHECK: S_NOP
> -# CHECK: S_NOP 0, implicit %sgpr0
> -# CHECK: S_NOP 0, implicit %sgpr2
> +# CHECK: S_NOP 0, implicit renamable %sgpr0
> +# CHECK: S_NOP 0, implicit renamable %sgpr2
> name: func1
> tracksRegLiveness: true
> body: |
> @@ -67,8 +67,8 @@ body: |
> # Check that copy hoisting out of loops works. This mainly should not crash the
> # compiler when it hoists a subreg copy sequence.
> # CHECK-LABEL: name: splitHoist
> -# CHECK: S_NOP 0, implicit-def %sgpr0
> -# CHECK: S_NOP 0, implicit-def %sgpr3
> +# CHECK: S_NOP 0, implicit-def renamable %sgpr0
> +# CHECK: S_NOP 0, implicit-def renamable %sgpr3
> # CHECK-NEXT: SI_SPILL_S128_SAVE
> name: splitHoist
> tracksRegLiveness: true
>
> Modified: llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir?rev=320503&r1=320502&r2=320503&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir (original)
> +++ llvm/trunk/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir Tue Dec 12 09:53:59 2017
> @@ -9,10 +9,10 @@
> # CHECK: - { id: 1, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
> # CHECK-NEXT: stack-id: 1,
>
> -# CHECK: SI_SPILL_V32_SAVE killed %vgpr0, %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (store 4 into %stack.0)
> +# CHECK: SI_SPILL_V32_SAVE killed renamable %vgpr0, %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (store 4 into %stack.0)
> # CHECK: %vgpr0 = SI_SPILL_V32_RESTORE %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (load 4 from %stack.0)
>
> -# CHECK: SI_SPILL_S32_SAVE killed %sgpr6, %stack.1, implicit %exec, implicit %sgpr0_sgpr1_sgpr2_sgpr3, implicit %sgpr5, implicit-def dead %m0 :: (store 4 into %stack.1)
> +# CHECK: SI_SPILL_S32_SAVE killed renamable %sgpr6, %stack.1, implicit %exec, implicit %sgpr0_sgpr1_sgpr2_sgpr3, implicit %sgpr5, implicit-def dead %m0 :: (store 4 into %stack.1)
> # CHECK: %sgpr6 = SI_SPILL_S32_RESTORE %stack.1, implicit %exec, implicit %sgpr0_sgpr1_sgpr2_sgpr3, implicit %sgpr5, implicit-def dead %m0 :: (load 4 from %stack.1)
>
> name: no_merge_sgpr_vgpr_spill_slot
>
> Modified: llvm/trunk/test/CodeGen/AMDGPU/subreg_interference.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/subreg_interference.mir?rev=320503&r1=320502&r2=320503&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AMDGPU/subreg_interference.mir (original)
> +++ llvm/trunk/test/CodeGen/AMDGPU/subreg_interference.mir Tue Dec 12 09:53:59 2017
> @@ -12,12 +12,12 @@
> # sgpr0-sgpr3.
> #
> # CHECK-LABEL: func0
> -# CHECK: S_NOP 0, implicit-def %sgpr0
> -# CHECK: S_NOP 0, implicit-def %sgpr3
> -# CHECK: S_NOP 0, implicit-def %sgpr1
> -# CHECK: S_NOP 0, implicit-def %sgpr2
> -# CHECK: S_NOP 0, implicit %sgpr0, implicit %sgpr3
> -# CHECK: S_NOP 0, implicit %sgpr1, implicit %sgpr2
> +# CHECK: S_NOP 0, implicit-def renamable %sgpr0
> +# CHECK: S_NOP 0, implicit-def renamable %sgpr3
> +# CHECK: S_NOP 0, implicit-def renamable %sgpr1
> +# CHECK: S_NOP 0, implicit-def renamable %sgpr2
> +# CHECK: S_NOP 0, implicit renamable %sgpr0, implicit renamable %sgpr3
> +# CHECK: S_NOP 0, implicit renamable %sgpr1, implicit renamable %sgpr2
> name: func0
> body: |
> bb.0:
>
> Modified: llvm/trunk/test/CodeGen/AMDGPU/syncscopes.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/syncscopes.ll?rev=320503&r1=320502&r2=320503&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AMDGPU/syncscopes.ll (original)
> +++ llvm/trunk/test/CodeGen/AMDGPU/syncscopes.ll Tue Dec 12 09:53:59 2017
> @@ -1,9 +1,9 @@
> ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -stop-before=si-debugger-insert-nops < %s | FileCheck --check-prefix=GCN %s
>
> ; GCN-LABEL: name: syncscopes
> -; GCN: FLAT_STORE_DWORD killed %vgpr1_vgpr2, killed %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("agent") seq_cst 4 into %ir.agent_out)
> -; GCN: FLAT_STORE_DWORD killed %vgpr4_vgpr5, killed %vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out)
> -; GCN: FLAT_STORE_DWORD killed %vgpr7_vgpr8, killed %vgpr6, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out)
> +; GCN: FLAT_STORE_DWORD killed renamable %vgpr1_vgpr2, killed renamable %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("agent") seq_cst 4 into %ir.agent_out)
> +; GCN: FLAT_STORE_DWORD killed renamable %vgpr4_vgpr5, killed renamable %vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out)
> +; GCN: FLAT_STORE_DWORD killed renamable %vgpr7_vgpr8, killed renamable %vgpr6, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out)
> define void @syncscopes(
> i32 %agent,
> i32 addrspace(4)* %agent_out,
>
> Modified: llvm/trunk/test/CodeGen/Hexagon/regalloc-bad-undef.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/regalloc-bad-undef.mir?rev=320503&r1=320502&r2=320503&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Hexagon/regalloc-bad-undef.mir (original)
> +++ llvm/trunk/test/CodeGen/Hexagon/regalloc-bad-undef.mir Tue Dec 12 09:53:59 2017
> @@ -153,7 +153,7 @@ body: |
> %13 = S2_asl_r_p_acc %13, %47, %8.isub_lo
> %51 = A2_tfrpi 0
>
> - ; CHECK: %d2 = S2_extractup undef %d0, 6, 25
> + ; CHECK: %d2 = S2_extractup undef renamable %d0, 6, 25
> ; CHECK: %d0 = A2_tfrpi 2
> ; CHECK: %d13 = A2_tfrpi -1
> ; CHECK-NOT: undef %r4
>
> Added: llvm/trunk/test/CodeGen/MIR/X86/renamable-register-flag.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/renamable-register-flag.mir?rev=320503&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/MIR/X86/renamable-register-flag.mir (added)
> +++ llvm/trunk/test/CodeGen/MIR/X86/renamable-register-flag.mir Tue Dec 12 09:53:59 2017
> @@ -0,0 +1,16 @@
> +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
> +# This test ensures that the MIR parser parses the 'renamable' register flags
> +# correctly.
> +
> +--- |
> + define void @foo() { ret void }
> +...
> +---
> +name: foo
> +body: |
> + ; CHECK: bb.0:
> + bb.0:
> + ; CHECK: renamable %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags
> + renamable %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags
> + RETQ %eax
> +...
>
> Modified: llvm/trunk/test/CodeGen/PowerPC/byval-agg-info.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/byval-agg-info.ll?rev=320503&r1=320502&r2=320503&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/byval-agg-info.ll (original)
> +++ llvm/trunk/test/CodeGen/PowerPC/byval-agg-info.ll Tue Dec 12 09:53:59 2017
> @@ -13,5 +13,5 @@ entry:
>
> ; Make sure that the MMO on the store has no offset from the byval
> ; variable itself (we used to have mem:ST8[%v+64]).
> -; CHECK: STD killed %x5, 176, %x1; mem:ST8[%v](align=16)
> +; CHECK: STD killed renamable %x5, 176, %x1; mem:ST8[%v](align=16)
>
>
> Modified: llvm/trunk/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir?rev=320503&r1=320502&r2=320503&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir (original)
> +++ llvm/trunk/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir Tue Dec 12 09:53:59 2017
> @@ -18,11 +18,11 @@ registers:
> - { id: 1, class: gr64bit }
> - { id: 2, class: addr64bit }
> # CHECK: %r0q = L128
> -# CHECK-NEXT: %r0l = COPY %r1l
> +# CHECK-NEXT: %r0l = COPY renamable %r1l
> # Although R0L partially redefines R0Q, it must not mark R0Q as kill
> # because R1D is still live through that instruction.
> # CHECK-NOT: implicit killed %r0q
> -# CHECK-NEXT: %r2d = COPY %r1d
> +# CHECK-NEXT: %r2d = COPY renamable %r1d
> # CHECK-NEXT: LARL
> body: |
> bb.0:
>
> Modified: llvm/trunk/test/CodeGen/X86/tail-merge-debugloc.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tail-merge-debugloc.ll?rev=320503&r1=320502&r2=320503&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/tail-merge-debugloc.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/tail-merge-debugloc.ll Tue Dec 12 09:53:59 2017
> @@ -6,7 +6,7 @@
> ; location info.
> ;
> ; CHECK: [[DLOC:![0-9]+]] = !DILocation(line: 2, column: 2, scope: !{{[0-9]+}})
> -; CHECK: TEST64rr{{.*}}%rsi, %rsi, implicit-def %eflags
> +; CHECK: TEST64rr{{.*}}%rsi, renamable %rsi, implicit-def %eflags
> ; CHECK-NEXT: JNE_1{{.*}}, debug-location [[DLOC]]
>
> target triple = "x86_64-unknown-linux-gnu"
>
> Modified: llvm/trunk/test/DebugInfo/X86/pr34545.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/pr34545.ll?rev=320503&r1=320502&r2=320503&view=diff
> ==============================================================================
> --- llvm/trunk/test/DebugInfo/X86/pr34545.ll (original)
> +++ llvm/trunk/test/DebugInfo/X86/pr34545.ll Tue Dec 12 09:53:59 2017
> @@ -2,11 +2,11 @@
>
> ; CHECK: %eax = MOV32rm
> ; CHECK: DBG_VALUE %eax
> -; CHECK: %eax = SHL32rCL killed %eax
> +; CHECK: %eax = SHL32rCL killed renamable %eax
> ; CHECK: DBG_VALUE %eax
> ; CHECK: DBG_VALUE %rsp, 0, !{{[0-9]+}}, !DIExpression(DW_OP_constu, 4, DW_OP_minus)
> ; CHECK: DBG_VALUE %eax
> -; CHECK: %eax = SHL32rCL killed %eax
> +; CHECK: %eax = SHL32rCL killed renamable %eax
> ; CHECK: DBG_VALUE %eax
> ; CHECK: RETQ %eax
>
>
> Modified: llvm/trunk/test/DebugInfo/X86/sdag-salvage-add.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/sdag-salvage-add.ll?rev=320503&r1=320502&r2=320503&view=diff
> ==============================================================================
> --- llvm/trunk/test/DebugInfo/X86/sdag-salvage-add.ll (original)
> +++ llvm/trunk/test/DebugInfo/X86/sdag-salvage-add.ll Tue Dec 12 09:53:59 2017
> @@ -28,7 +28,7 @@
> ; CHECK-SAME: !DIExpression(DW_OP_plus_uconst, 4096, DW_OP_stack_value)
> ; CHECK-NEXT: DBG_VALUE debug-use %rax, debug-use %noreg, ![[S4]],
> ; CHECK-SAME: !DIExpression(DW_OP_plus_uconst, 4096, DW_OP_stack_value)
> -; CHECK-NEXT: %rdi = MOV64rm killed %rax, 1, %noreg, 4096, %noreg,
> +; CHECK-NEXT: %rdi = MOV64rm killed renamable %rax, 1, %noreg, 4096, %noreg,
>
> source_filename = "test.c"
> target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
>
>
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