[PATCH] D43201: [X86] Only reorder srl/and on last DAG combiner run

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

I've committed the test case, and this patch had no effect on it.



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Comment at: test/CodeGen/X86/test-vs-bittest.ll:55
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    testl $2048, %edi # imm = 0x800
 ; CHECK-NEXT:    je .LBB2_2
----------------
Note this test is identical to test64 above with the operands of the 'br' instruction reversed. We were always using 'test'. Seems the initial selectionDAG in one of the cases(i forgot which one) has an ISD::XOR inverting the setcc result before the branch. This somehow causes a difference in DAG combine ordering or something that leads to different results.


https://reviews.llvm.org/D43201