[PATCH] D43201: [X86] Only reorder srl/and on last DAG combiner run

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

In https://reviews.llvm.org/D43201#1009165, @reames wrote:

> In https://reviews.llvm.org/D43201#1008877, @davezarzycki wrote:
>
> > (Beyond the scope of this patch…) I wish LLVM or the x86 backend could change its instruction selection on the fly. Then it could prefer "reasonable density" (not microcoded) by default and "throughput" in loops (or otherwise obvious hot paths). This would probably yield the best overall/pragmatic performance.
>
>
> Just to second this, I think there's a lot of potential gain to be had by being able to select cold blocks for size and hot blocks for speed.  As stated, definitely off topic for this review though!


@davezarzycki  @reames Any chance that you could put some of this request into a bugzilla please? Its the kind of thing that keeps getting bounced around for scheduler driven MC optimizations.


https://reviews.llvm.org/D43201