[PATCH] D41651: AMDGPU: Add 32-bit constant address space
Marek Olšák via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 15 04:40:39 PST 2018
mareko added a comment.
In https://reviews.llvm.org/D41651#1008600, @alex-t wrote:
> In fact v_readfirstlane is inserted by the ISel to glue vector input to the unexpected scalar instruction.
> This means that compiler user writing valid IR will get unexpected behavior.
> Is this documented somewhere?
>
> My objections WRT implementation are:
> Bypassing the normal way of processing values divergence is misleading. I was very much surprised to see "amdgpu.uniform" metadata already set at the point (AMDGPUAnnotateUniformValues) where they are expected to be queried from DA.
> Moreover they were set for the value that is reported by DA as divergent!
The address space is meant to be used for loading shader resource descriptors. It's not a general-purpose address space.
Repository:
rL LLVM
https://reviews.llvm.org/D41651
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