[PATCH] D41651: AMDGPU: Add 32-bit constant address space
Marek Olšák via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 14 15:18:57 PST 2018
mareko added inline comments.
================
Comment at: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:232
+ if (MMO->getAddrSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT)
+ return true;
----------------
alex-t wrote:
> Is it still uniform even if depends on divergent data?
> Like this:
> %tid = tail call i32 @llvm.amdgcn.workgroup.id.x()
> %gep = getelementptr i32 addrspace(6)* %tid
> %val = load i32, i32 addrspace(6)* %gep
>
> This is not correct
> Moreover, this violates Divergence Analysis results
The address space implies uniformity and is geared towards shader resource descriptor loads where uniformity is required. Non-uniform addresses result in v_readfirstlane. In the future, the implementation can be extended to support non-divergent data and VMEM loads/stores/atomics.
Repository:
rL LLVM
https://reviews.llvm.org/D41651
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