[llvm] r325153 - [RegisterClassInfo] Invalidate the register pressure set limit cache when reserved regs or callee saved regs change

[Craig Topper via llvm-commits]

Author: ctopper
Date: Wed Feb 14 10:53:29 2018
New Revision: 325153

URL: http://llvm.org/viewvc/llvm-project?rev=325153&view=rev
Log:
[RegisterClassInfo] Invalidate the register pressure set limit cache when reserved regs or callee saved regs change

Previously we only invalidated the pressure set limit cached when the TargetRegisterInfo pointer changes. But as reserved regs and callee saved regs are used as part of calculating the limits we should invalidate when those change too.

I encountered this when reverting a patch from the 6.0 branch. One of the x86 test files had a function that used rbp as a frame pointer, making it reserved. It was followed by another function which didn't use rbp but had the same TRI so the pressure set limit cache was not invalidated. If i removed the function that used rbp as a frame pointer from the file, the remaining function then got a different register pressure limit for the GR16 pressure set. This caused the machine scheduler to change the scheduling for the function. This was an unexpected change from just deleting a function.

I don't have a test case for trunk because the particular x86 test case is different enough from the 6.0 branch to not be affected now.

Differential Revision: https://reviews.llvm.org/D43274

Modified:
    llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp

Modified: llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp?rev=325153&r1=325152&r2=325153&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp Wed Feb 14 10:53:29 2018
@@ -49,9 +49,6 @@ void RegisterClassInfo::runOnMachineFunc
   if (MF->getSubtarget().getRegisterInfo() != TRI) {
     TRI = MF->getSubtarget().getRegisterInfo();
     RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
-    unsigned NumPSets = TRI->getNumRegPressureSets();
-    PSetLimits.reset(new unsigned[NumPSets]);
-    std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
     Update = true;
   }
 
@@ -80,8 +77,12 @@ void RegisterClassInfo::runOnMachineFunc
   }
 
   // Invalidate cached information from previous function.
-  if (Update)
+  if (Update) {
+    unsigned NumPSets = TRI->getNumRegPressureSets();
+    PSetLimits.reset(new unsigned[NumPSets]);
+    std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
     ++Tag;
+  }
 }
 
 /// compute - Compute the preferred allocation order for RC with reserved