[PATCH] D43170: [AMDGPU] Change constant addr space to 4

[Yaxun Liu via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL325030: [AMDGPU] Change constant addr space to 4 (authored by yaxunl, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D43170?vs=133801&id=134069#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D43170

Files:
  llvm/trunk/docs/AMDGPUUsage.rst
  llvm/trunk/include/llvm/IR/IntrinsicsAMDGPU.td
  llvm/trunk/lib/Target/AMDGPU/AMDGPU.h
  llvm/trunk/lib/Target/AMDGPU/AMDGPUAliasAnalysis.cpp
  llvm/trunk/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
  llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  llvm/trunk/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
  llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
  llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
  llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir
  llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/smrd.ll
  llvm/trunk/test/CodeGen/AMDGPU/add.v2i16.ll
  llvm/trunk/test/CodeGen/AMDGPU/addrspacecast.ll
  llvm/trunk/test/CodeGen/AMDGPU/amdgcn.bitcast.ll
  llvm/trunk/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
  llvm/trunk/test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll
  llvm/trunk/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll
  llvm/trunk/test/CodeGen/AMDGPU/branch-relaxation.ll
  llvm/trunk/test/CodeGen/AMDGPU/call-argument-types.ll
  llvm/trunk/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll
  llvm/trunk/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll
  llvm/trunk/test/CodeGen/AMDGPU/cgp-addressing-modes.ll
  llvm/trunk/test/CodeGen/AMDGPU/early-if-convert-cost.ll
  llvm/trunk/test/CodeGen/AMDGPU/early-if-convert.ll
  llvm/trunk/test/CodeGen/AMDGPU/extract_vector_elt-f16.ll
  llvm/trunk/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll
  llvm/trunk/test/CodeGen/AMDGPU/fence-barrier.ll
  llvm/trunk/test/CodeGen/AMDGPU/function-returns.ll
  llvm/trunk/test/CodeGen/AMDGPU/global-constant.ll
  llvm/trunk/test/CodeGen/AMDGPU/gv-const-addrspace.ll
  llvm/trunk/test/CodeGen/AMDGPU/hsa-func-align.ll
  llvm/trunk/test/CodeGen/AMDGPU/hsa-func.ll
  llvm/trunk/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ir-full.ll
  llvm/trunk/test/CodeGen/AMDGPU/image-schedule.ll
  llvm/trunk/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
  llvm/trunk/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll
  llvm/trunk/test/CodeGen/AMDGPU/llvm.SI.load.dword.ll
  llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.ptr.ll
  llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.buffer.ptr.hsa.ll
  llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.buffer.ptr.ll
  llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
  llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll
  llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll
  llvm/trunk/test/CodeGen/AMDGPU/llvm.memcpy.ll
  llvm/trunk/test/CodeGen/AMDGPU/load-constant-f64.ll
  llvm/trunk/test/CodeGen/AMDGPU/load-constant-i1.ll
  llvm/trunk/test/CodeGen/AMDGPU/load-constant-i16.ll
  llvm/trunk/test/CodeGen/AMDGPU/load-constant-i32.ll
  llvm/trunk/test/CodeGen/AMDGPU/load-constant-i64.ll
  llvm/trunk/test/CodeGen/AMDGPU/load-constant-i8.ll
  llvm/trunk/test/CodeGen/AMDGPU/load-hi16.ll
  llvm/trunk/test/CodeGen/AMDGPU/load-lo16.ll
  llvm/trunk/test/CodeGen/AMDGPU/mad24-get-global-id.ll
  llvm/trunk/test/CodeGen/AMDGPU/missing-store.ll
  llvm/trunk/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll
  llvm/trunk/test/CodeGen/AMDGPU/mubuf.ll
  llvm/trunk/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
  llvm/trunk/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll
  llvm/trunk/test/CodeGen/AMDGPU/no-shrink-extloads.ll
  llvm/trunk/test/CodeGen/AMDGPU/nullptr.ll
  llvm/trunk/test/CodeGen/AMDGPU/pack.v2f16.ll
  llvm/trunk/test/CodeGen/AMDGPU/pack.v2i16.ll
  llvm/trunk/test/CodeGen/AMDGPU/r600-constant-array-fixup.ll
  llvm/trunk/test/CodeGen/AMDGPU/readcyclecounter.ll
  llvm/trunk/test/CodeGen/AMDGPU/ret.ll
  llvm/trunk/test/CodeGen/AMDGPU/salu-to-valu.ll
  llvm/trunk/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
  llvm/trunk/test/CodeGen/AMDGPU/sext-in-reg.ll
  llvm/trunk/test/CodeGen/AMDGPU/sgpr-copy.ll
  llvm/trunk/test/CodeGen/AMDGPU/si-lod-bias.ll
  llvm/trunk/test/CodeGen/AMDGPU/si-scheduler.ll
  llvm/trunk/test/CodeGen/AMDGPU/si-sgpr-spill.ll
  llvm/trunk/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
  llvm/trunk/test/CodeGen/AMDGPU/smrd-vccz-bug.ll
  llvm/trunk/test/CodeGen/AMDGPU/smrd.ll
  llvm/trunk/test/CodeGen/AMDGPU/spill-m0.ll
  llvm/trunk/test/CodeGen/AMDGPU/split-smrd.ll
  llvm/trunk/test/CodeGen/AMDGPU/store-global.ll
  llvm/trunk/test/CodeGen/AMDGPU/store-private.ll
  llvm/trunk/test/CodeGen/AMDGPU/sub.v2i16.ll
  llvm/trunk/test/CodeGen/AMDGPU/target-cpu.ll
  llvm/trunk/test/CodeGen/AMDGPU/unaligned-load-store.ll
  llvm/trunk/test/CodeGen/AMDGPU/uniform-crash.ll
  llvm/trunk/test/CodeGen/AMDGPU/vertex-fetch-encoding.ll
  llvm/trunk/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
  llvm/trunk/test/CodeGen/AMDGPU/wait.ll
  llvm/trunk/test/CodeGen/AMDGPU/waitcnt-looptest.ll
  llvm/trunk/test/CodeGen/AMDGPU/widen_extending_scalar_loads.ll
  llvm/trunk/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn-addrspace-addressing-modes.ll

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