[PATCH] D35267: Pass Divergence Analysis data to selection DAG to drive divergence dependent instruction selection

[Alexander via Phabricator via llvm-commits]

alex-t added inline comments.


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Comment at: lib/Target/AMDGPU/AMDGPUISelLowering.cpp:781
+        if (RI->isPhysicalRegister(Reg)) {
+          return RI->getRegClass(AMDGPU::VGPR_32RegClassID)->contains(Reg) ||
+            RI->getRegClass(AMDGPU::VReg_64RegClassID)->contains(Reg) ||
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rampitec wrote:
> SIRegisterInfo::isVGPR()
What should we do fro R600Subtarget?


https://reviews.llvm.org/D35267