[PATCH] D42962: [ARM] Allow 64- and 128-bit types with 't' inline asm constraint

[Pablo Barrio via Phabricator via llvm-commits]

pbarrio added a comment.

There is still the possibility that someone tries to use 't' for a vector of two doubles. Only single-precision is allowed in vector operations for 32-bit architectures, so doing something like this would be illegal:

\_\_asm\_\_ ("vadd.f64 %0, %1, %2" : "=t" (res) : "t" (a), "t" (b));

like @rengolin pointed out earlier on.

In this case, the constraint handling code will happily allocate a Q register, but the compiler will fail with the following:

<inline asm>:1:6: error: invalid operand for instruction

  vadd.f64 q0, q0, q1

I think we don't need a new test for this case because this is already taken care of by the MC testing of instruction encodings.

Besides, I would argue that someone trying to pass a vector of doubles to vadd.f64 (or any other 32-bit ARM vector instruction) is doing something incorrect, but this is not a problem of the register constraint itself. Note that this problem also predates this patch, as the 'w' constraint also suffers from it.

Does this sound reasonable?


Repository:
  rL LLVM

https://reviews.llvm.org/D42962