[llvm] r324986 - [X86] Add a blsr test case with a shift from PR35792. NFC

[Craig Topper via llvm-commits]

Author: ctopper
Date: Mon Feb 12 21:33:39 2018
New Revision: 324986

URL: http://llvm.org/viewvc/llvm-project?rev=324986&view=rev
Log:
[X86] Add a blsr test case with a shift from PR35792. NFC

The blsr pattern here is missed because the add is shrunk, but the and is not. This leaves an any_extend between them.

Modified:
    llvm/trunk/test/CodeGen/X86/bmi.ll

Modified: llvm/trunk/test/CodeGen/X86/bmi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi.ll?rev=324986&r1=324985&r2=324986&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bmi.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bmi.ll Mon Feb 12 21:33:39 2018
@@ -822,3 +822,16 @@ define i64 @blsr_disguised_constant(i64
   ret i64 %r
 }
 
+; The add here gets shrunk, but the and does not thus hiding the blsr pattern.
+define i64 @blsr_disguised_shrunk_add(i64 %x) {
+; CHECK-LABEL: blsr_disguised_shrunk_add:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    shrq $48, %rdi
+; CHECK-NEXT:    leal -1(%rdi), %eax
+; CHECK-NEXT:    andq %rdi, %rax
+; CHECK-NEXT:    retq
+  %a = lshr i64 %x, 48
+  %b = add i64 %a, -1
+  %c = and i64 %b, %a
+  ret i64 %c
+}