[PATCH] D42962: [ARM] Allow 64- and 128-bit types with 't' inline asm constraint

[Pablo Barrio via Phabricator via llvm-commits]

pbarrio added a comment.

In https://reviews.llvm.org/D42962#1005332, @rengolin wrote:

> In https://reviews.llvm.org/D42962#1005311, @pbarrio wrote:
>
> > I was wrong when I said the GNU modifiers are q/e, which actually makes things easier. The correct operand modifiers to select a quad/double vector register in GCC are q/P. These already work in LLVM (they are just ignored according to the documentation and also my local testing). So, I think there is no need for an additional patch; we should be able to handle inline assembly written for GCC with the 't' constraint.
>
>
> I'm not sure I get this. Are you saying this patch can be abandoned?


No, this patch (register constraints) is still ok. @efriedma argued that the patch would not make LLVM accept inline assembly from GCC, so he didn't see the point of it. This was because I mentioned that we would need another patch to support the operand modifiers. Now it turns out that the operand modifiers (q/P) are already accepted in LLVM, so no further work needed (apart from this patch).

Sorry, I was using the wrong operand modifiers in my GCC tests earlier on, so I thought they were not allowed in LLVM. q/P work fine in both GCC and LLVM.


Repository:
  rL LLVM

https://reviews.llvm.org/D42962