[PATCH] D43201: [X86] Only reorder srl/and on last DAG combiner run

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: spatel, RKSimon.

This seems to interfere with a target independent brcond combine that looks for the (srl (and X, C1), C2) pattern to enable TEST instructions. Once we flip, that combine doesn't fire and we end up exposing it to the X86 specific BT combine which causes us to emit a BT instruction. BT has lower throughput than TEST.

We could try to make the brcond combine aware of the alternate pattern, but since the flip was just a code size reduction and not likely to enable other combines, it seemed easier to just delay it until after lowering.


https://reviews.llvm.org/D43201

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/live-out-reg-info.ll
  test/CodeGen/X86/test-shrink.ll
  test/CodeGen/X86/xor-icmp.ll

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