[PATCH] D43179: [Thumb] Handle addressing mode AddrMode5FP16

[Oliver Stannard via Phabricator via llvm-commits]

olista01 added inline comments.


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Comment at: lib/Target/ARM/Thumb2InstrInfo.cpp:611
+      Scale = 2;
+      Offset += InstrOffs * 4;
+      assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
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Why is this multiplied by 4, and not 2?


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Comment at: test/CodeGen/ARM/fp16-instructions.ll:708
+  store volatile half 0xH3C00, half* %S, align 2
+  %S.0.S.0. = load volatile half, half* %S, align 2
+  %add = fadd half %S.0.S.0., %0
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There is a half-precision load in the IR, does this generate a vldr.16? if so, we should be checking that.


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Comment at: test/CodeGen/ARM/fp16-instructions.ll:715
+; CHECK-LABEL:            ThumbAddrMode5FP16
+; CHECK-SOFTFP-FULLFP16:  vstr.16 s0, [sp, #2]
+}
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This test will be fragile WRT changes in stack layout, so we should use a regex for the offset.


https://reviews.llvm.org/D43179