[llvm] r324898 - [X86] Tag CET-IBT instruction scheduler classes
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 12 07:57:00 PST 2018
Author: rksimon
Date: Mon Feb 12 07:57:00 2018
New Revision: 324898
URL: http://llvm.org/viewvc/llvm-project?rev=324898&view=rev
Log:
[X86] Tag CET-IBT instruction scheduler classes
Modified:
llvm/trunk/lib/Target/X86/X86InstrSystem.td
Modified: llvm/trunk/lib/Target/X86/X86InstrSystem.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSystem.td?rev=324898&r1=324897&r2=324898&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSystem.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSystem.td Mon Feb 12 07:57:00 2018
@@ -536,10 +536,10 @@ let SchedRW = [WriteSystem], Predicates
} // Defs SSP
} // SchedRW && HasSHSTK
-let Predicates = [HasIBT] in {
+let SchedRW = [WriteSystem], Predicates = [HasIBT] in {
def ENDBR64 : I<0x1E, MRM_FA, (outs), (ins), "endbr64", []>, XS;
def ENDBR32 : I<0x1E, MRM_FB, (outs), (ins), "endbr32", []>, XS;
-} // HasIBT
+} // SchedRW && HasIBT
//===----------------------------------------------------------------------===//
// XSAVE instructions
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