[PATCH] D42477: [AArch64] Improve v8.1-A code-gen for atomic load-subtract

[Christof Douma via Phabricator via llvm-commits]

christof added a comment.

On the previous review (https://reviews.llvm.org/D35375),  Geoff Berry suggested to do this in DAG Combine, to see if you can do some further combines, and suggested to not limit this to constants: https://reviews.llvm.org/D35375#810045

Did you consider those points?



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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:7394
 
+SDValue AArch64TargetLowering::LowerATOMIC_LOAD_SUB(SDValue Op,
+                                                    SelectionDAG &DAG) const {
----------------
Is there no (easy) way to do this in tablegen? I would prefer a tablegen pattern over C code. Even though this C looks nice and tidy.


Repository:
  rL LLVM

https://reviews.llvm.org/D42477