[PATCH] D42965: [CodeGen] Add a -trap-unreachable option for debugging

[Dave Green via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL324880: [CodeGen] Add a -trap-unreachable option for debugging (authored by dmgreen, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D42965?vs=133188&id=133824#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D42965

Files:
  llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
  llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp
  llvm/trunk/test/CodeGen/ARM/trap-unreachable.ll
  llvm/trunk/test/CodeGen/Hexagon/trap-unreachable.ll


Index: llvm/trunk/test/CodeGen/ARM/trap-unreachable.ll
===================================================================
--- llvm/trunk/test/CodeGen/ARM/trap-unreachable.ll
+++ llvm/trunk/test/CodeGen/ARM/trap-unreachable.ll
@@ -0,0 +1,8 @@
+; RUN: llc -mtriple=thumbv7 -trap-unreachable < %s | FileCheck %s
+; CHECK: .inst.n 0xdefe
+
+define void @test() #0 {
+  unreachable
+}
+
+attributes #0 = { nounwind }
Index: llvm/trunk/test/CodeGen/Hexagon/trap-unreachable.ll
===================================================================
--- llvm/trunk/test/CodeGen/Hexagon/trap-unreachable.ll
+++ llvm/trunk/test/CodeGen/Hexagon/trap-unreachable.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -hexagon-trap-unreachable < %s | FileCheck %s
+; RUN: llc -march=hexagon -trap-unreachable < %s | FileCheck %s
 ; CHECK: call abort
 
 define void @fred() #0 {
Index: llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
+++ llvm/trunk/lib/CodeGen/LLVMTargetMachine.cpp
@@ -34,6 +34,10 @@
 #include "llvm/Target/TargetOptions.h"
 using namespace llvm;
 
+static cl::opt<bool> EnableTrapUnreachable("trap-unreachable",
+  cl::Hidden, cl::ZeroOrMore, cl::init(false),
+  cl::desc("Enable generating trap for unreachable"));
+
 void LLVMTargetMachine::initAsmInfo() {
   MRI = TheTarget.createMCRegInfo(getTargetTriple().str());
   MII = TheTarget.createMCInstrInfo();
@@ -79,6 +83,9 @@
   this->RM = RM;
   this->CMModel = CM;
   this->OptLevel = OL;
+
+  if (EnableTrapUnreachable)
+    this->Options.TrapUnreachable = true;
 }
 
 TargetTransformInfo
Index: llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp
===================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp
+++ llvm/trunk/lib/Target/Hexagon/HexagonTargetMachine.cpp
@@ -97,10 +97,6 @@
 static cl::opt<bool> EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden,
   cl::ZeroOrMore, cl::init(true), cl::desc("Enable vextract optimization"));
 
-static cl::opt<bool> EnableTrapUnreachable("hexagon-trap-unreachable",
-  cl::Hidden, cl::ZeroOrMore, cl::init(false),
-  cl::desc("Enable generating trap for unreachable"));
-
 /// HexagonTargetMachineModule - Note that this is used on hosts that
 /// cannot link in a library unless there are references into the
 /// library.  In particular, it seems that it is not possible to get
@@ -219,8 +215,6 @@
           TT, CPU, FS, Options, getEffectiveRelocModel(RM),
           getEffectiveCodeModel(CM), (HexagonNoOpt ? CodeGenOpt::None : OL)),
       TLOF(make_unique<HexagonTargetObjectFile>()) {
-  if (EnableTrapUnreachable)
-    this->Options.TrapUnreachable = true;
   initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
   initAsmInfo();
 }


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