[llvm] r324856 - [X86] Remove LowerBoolVSETCC_AVX512, we get this with a target independent DAG combine now. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 11 14:32:27 PST 2018
Author: ctopper
Date: Sun Feb 11 14:32:27 2018
New Revision: 324856
URL: http://llvm.org/viewvc/llvm-project?rev=324856&view=rev
Log:
[X86] Remove LowerBoolVSETCC_AVX512, we get this with a target independent DAG combine now. NFC
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=324856&r1=324855&r2=324856&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Feb 11 14:32:27 2018
@@ -17799,49 +17799,6 @@ static SDValue Lower256IntVSETCC(SDValue
DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
}
-static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
- SDValue Op0 = Op.getOperand(0);
- SDValue Op1 = Op.getOperand(1);
- SDValue CC = Op.getOperand(2);
- MVT VT = Op.getSimpleValueType();
- SDLoc dl(Op);
-
- assert(Op0.getSimpleValueType().getVectorElementType() == MVT::i1 &&
- "Unexpected type for boolean compare operation");
- ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
- SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
- DAG.getConstant(-1, dl, VT));
- SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
- DAG.getConstant(-1, dl, VT));
- switch (SetCCOpcode) {
- default: llvm_unreachable("Unexpected SETCC condition");
- case ISD::SETEQ:
- // (x == y) -> ~(x ^ y)
- return DAG.getNode(ISD::XOR, dl, VT,
- DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
- DAG.getConstant(-1, dl, VT));
- case ISD::SETNE:
- // (x != y) -> (x ^ y)
- return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
- case ISD::SETUGT:
- case ISD::SETGT:
- // (x > y) -> (x & ~y)
- return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
- case ISD::SETULT:
- case ISD::SETLT:
- // (x < y) -> (~x & y)
- return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
- case ISD::SETULE:
- case ISD::SETLE:
- // (x <= y) -> (~x | y)
- return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
- case ISD::SETUGE:
- case ISD::SETGE:
- // (x >=y) -> (x | ~y)
- return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
- }
-}
-
static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
SDValue Op0 = Op.getOperand(0);
@@ -18013,16 +17970,11 @@ static SDValue LowerVSETCC(SDValue Op, c
if (VT.is256BitVector() && !Subtarget.hasInt256())
return Lower256IntVSETCC(Op, DAG);
- // Operands are boolean (vectors of i1)
- MVT OpVT = Op1.getSimpleValueType();
- if (OpVT.getVectorElementType() == MVT::i1)
- return LowerBoolVSETCC_AVX512(Op, DAG);
-
// The result is boolean, but operands are int/float
if (VT.getVectorElementType() == MVT::i1) {
// In AVX-512 architecture setcc returns mask with i1 elements,
// But there is no compare instruction for i8 and i16 elements in KNL.
- assert((OpVT.getScalarSizeInBits() >= 32 || Subtarget.hasBWI()) &&
+ assert((VTOp0.getScalarSizeInBits() >= 32 || Subtarget.hasBWI()) &&
"Unexpected operand type");
return LowerIntVSETCC_AVX512(Op, DAG);
}
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