[PATCH] D42724: [X86] Don't make 512-bit vectors legal when preferred vector width is 256 bits and 512 bits aren't required

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon accepted this revision.
RKSimon added a comment.
This revision is now accepted and ready to land.

LGTM as a first step - a few minors to explain the meaning of a lot of this.



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Comment at: lib/Target/X86/X86ISelLowering.cpp:1140
 
   if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
     addRegisterClass(MVT::v1i1,   &X86::VK1RegClass);
----------------
Comments explaining that we only legalize mask registers for hasAVX512, with the vector registers requiring useAVX512Regs


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Comment at: lib/Target/X86/X86ISelLowering.cpp:1156
     setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v4i1,  MVT::v4i32);
     setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v4i1,  MVT::v4i32);
     setOperationAction(ISD::SINT_TO_FP,         MVT::v2i1,  Custom);
----------------
Add tests for these since they touch 512-bit types.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:1165
     setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v4i1,  MVT::v4i32);
     setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v4i1,  MVT::v4i32);
     if (Subtarget.hasVLX()) {
----------------
Add tests for these since they touch 512-bit types.


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Comment at: lib/Target/X86/X86ISelLowering.cpp:1447
+
+    addRegisterClass(MVT::v64i1,  &X86::VK64RegClass);
+
----------------
Similar comment for 512-bit bw types and explain why v64i1 mask register isn't enabled with hasBWI


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Comment at: lib/Target/X86/X86ISelLowering.cpp:1533
 
-  if (!Subtarget.useSoftFloat() && Subtarget.hasBWI() &&
-      (Subtarget.hasAVX512() || Subtarget.hasVLX())) {
+  if (!Subtarget.useSoftFloat() && Subtarget.hasBWI()) {
     for (auto VT : { MVT::v32i8, MVT::v16i8, MVT::v16i16, MVT::v8i16 }) {
----------------
This change looks independent? If so commit it separately.


https://reviews.llvm.org/D42724