[PATCH] D43141: [DAG] make binops with undef operands consistent with IR

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Some of the test changes are a little iffy... we might want to adjust the to stop using undef rather than just change the expected result, to try to preserve some of the original intent.



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Comment at: lib/CodeGen/SelectionDAG/SelectionDAG.cpp:4713
     case ISD::AND:
-    case ISD::SRL:
-    case ISD::SHL:
-      if (!VT.isVector())
-        return getConstant(0, DL, VT);  // fold op(arg1, undef) -> 0
-      // For vectors, we can't easily build an all zero vector, just return
-      // the LHS.
-      return N1;
+      return getConstant(0, DL, VT);  // fold op(arg1, undef) -> 0
     case ISD::OR:
----------------
"For vectors, we can't easily build an all zero vector" doesn't mean that it's hard to construct a BUILD_VECTOR; the problem is ensuring we lower it before we run selection.  But it might not be a problem anymore because DAGCombine calls the legalizer?


https://reviews.llvm.org/D43141