[llvm] r324766 - [AArch64] Adjust the cost model for Exynos M3

[Evandro Menezes via llvm-commits]

Author: evandro
Date: Fri Feb  9 11:26:11 2018
New Revision: 324766

URL: http://llvm.org/viewvc/llvm-project?rev=324766&view=rev
Log:
[AArch64] Adjust the cost model for Exynos M3

Fix the modeling of transfers between a generic register and a partial ASIMD
one.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td?rev=324766&r1=324765&r2=324766&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedExynosM3.td Fri Feb  9 11:26:11 2018
@@ -287,6 +287,9 @@ def M3WriteNEOND   : SchedWriteRes<[M3Un
 def M3WriteNEONH   : SchedWriteRes<[M3UnitNALU,
                                     M3UnitS]>     { let Latency = 5;
                                                     let NumMicroOps = 2; }
+def M3WriteNEONI   : SchedWriteRes<[M3UnitNSHF,
+                                    M3UnitS]>     { let Latency = 5;
+                                                    let NumMicroOps = 2; }
 def M3WriteNEONV   : SchedWriteRes<[M3UnitFDIV,
                                     M3UnitFDIV]>  { let Latency = 7;
                                                     let NumMicroOps = 1;
@@ -527,8 +530,9 @@ def : InstRW<[M3WriteFCVT4],  (instregex
 def : InstRW<[M3WriteNMSC1],  (instregex "^FRECPXv1")>;
 def : InstRW<[M3WriteFMAC4,
               M3ReadFMAC],    (instregex "^F(RECP|RSQRT)S(16|32|64)")>;
-def : InstRW<[M3WriteNALU1],  (instregex "^FMOV[WX][DS](High)?r")>;
-def : InstRW<[M3WriteNALU1],  (instregex "^FMOV[DS][WX](High)?r")>;
+def : InstRW<[M3WriteNALU1],  (instregex "^FMOV[WX][DS]r")>;
+def : InstRW<[M3WriteNALU1],  (instregex "^FMOV[DS][WX]r")>;
+def : InstRW<[M3WriteNEONI],  (instregex "^FMOV(DX|XD)Highr")>;
 
 // FP load instructions.
 def : InstRW<[WriteVLD],    (instregex "^LDR[DSQ]l")>;