[llvm] r324745 - [AArch64] Refactor stand alone methods (NFC)
Evandro Menezes via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 9 08:14:41 PST 2018
Author: evandro
Date: Fri Feb 9 08:14:41 2018
New Revision: 324745
URL: http://llvm.org/viewvc/llvm-project?rev=324745&view=rev
Log:
[AArch64] Refactor stand alone methods (NFC)
Make stand alone methods in AArch64InstrInfo static.
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=324745&r1=324744&r2=324745&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp Fri Feb 9 08:14:41 2018
@@ -1607,7 +1607,7 @@ bool AArch64InstrInfo::expandPostRAPseud
}
/// Return true if this is this instruction has a non-zero immediate
-bool AArch64InstrInfo::hasShiftedReg(const MachineInstr &MI) const {
+bool AArch64InstrInfo::hasShiftedReg(const MachineInstr &MI) {
switch (MI.getOpcode()) {
default:
break;
@@ -1645,7 +1645,7 @@ bool AArch64InstrInfo::hasShiftedReg(con
}
/// Return true if this is this instruction has a non-zero immediate
-bool AArch64InstrInfo::hasExtendedReg(const MachineInstr &MI) const {
+bool AArch64InstrInfo::hasExtendedReg(const MachineInstr &MI) {
switch (MI.getOpcode()) {
default:
break;
@@ -1673,7 +1673,7 @@ bool AArch64InstrInfo::hasExtendedReg(co
// Return true if this instruction simply sets its single destination register
// to zero. This is equivalent to a register rename of the zero-register.
-bool AArch64InstrInfo::isGPRZero(const MachineInstr &MI) const {
+bool AArch64InstrInfo::isGPRZero(const MachineInstr &MI) {
switch (MI.getOpcode()) {
default:
break;
@@ -1697,7 +1697,7 @@ bool AArch64InstrInfo::isGPRZero(const M
// Return true if this instruction simply renames a general register without
// modifying bits.
-bool AArch64InstrInfo::isGPRCopy(const MachineInstr &MI) const {
+bool AArch64InstrInfo::isGPRCopy(const MachineInstr &MI) {
switch (MI.getOpcode()) {
default:
break;
@@ -1727,7 +1727,7 @@ bool AArch64InstrInfo::isGPRCopy(const M
// Return true if this instruction simply renames a general register without
// modifying bits.
-bool AArch64InstrInfo::isFPRCopy(const MachineInstr &MI) const {
+bool AArch64InstrInfo::isFPRCopy(const MachineInstr &MI) {
switch (MI.getOpcode()) {
default:
break;
@@ -1796,7 +1796,7 @@ unsigned AArch64InstrInfo::isStoreToStac
/// Return true if this is load/store scales or extends its register offset.
/// This refers to scaling a dynamic index as opposed to scaled immediates.
/// MI should be a memory op that allows scaled addressing.
-bool AArch64InstrInfo::isScaledAddr(const MachineInstr &MI) const {
+bool AArch64InstrInfo::isScaledAddr(const MachineInstr &MI) {
switch (MI.getOpcode()) {
default:
break;
@@ -1855,27 +1855,27 @@ bool AArch64InstrInfo::isScaledAddr(cons
}
/// Check all MachineMemOperands for a hint to suppress pairing.
-bool AArch64InstrInfo::isLdStPairSuppressed(const MachineInstr &MI) const {
+bool AArch64InstrInfo::isLdStPairSuppressed(const MachineInstr &MI) {
return llvm::any_of(MI.memoperands(), [](MachineMemOperand *MMO) {
return MMO->getFlags() & MOSuppressPair;
});
}
/// Set a flag on the first MachineMemOperand to suppress pairing.
-void AArch64InstrInfo::suppressLdStPair(MachineInstr &MI) const {
+void AArch64InstrInfo::suppressLdStPair(MachineInstr &MI) {
if (MI.memoperands_empty())
return;
(*MI.memoperands_begin())->setFlags(MOSuppressPair);
}
/// Check all MachineMemOperands for a hint that the load/store is strided.
-bool AArch64InstrInfo::isStridedAccess(const MachineInstr &MI) const {
+bool AArch64InstrInfo::isStridedAccess(const MachineInstr &MI) {
return llvm::any_of(MI.memoperands(), [](MachineMemOperand *MMO) {
return MMO->getFlags() & MOStridedAccess;
});
}
-bool AArch64InstrInfo::isUnscaledLdSt(unsigned Opc) const {
+bool AArch64InstrInfo::isUnscaledLdSt(unsigned Opc) {
switch (Opc) {
default:
return false;
@@ -1900,8 +1900,124 @@ bool AArch64InstrInfo::isUnscaledLdSt(un
}
}
-bool AArch64InstrInfo::isUnscaledLdSt(MachineInstr &MI) const {
- return isUnscaledLdSt(MI.getOpcode());
+bool AArch64InstrInfo::isPairableLdStInst(const MachineInstr &MI) {
+ switch (MI.getOpcode()) {
+ default:
+ return false;
+ // Scaled instructions.
+ case AArch64::STRSui:
+ case AArch64::STRDui:
+ case AArch64::STRQui:
+ case AArch64::STRXui:
+ case AArch64::STRWui:
+ case AArch64::LDRSui:
+ case AArch64::LDRDui:
+ case AArch64::LDRQui:
+ case AArch64::LDRXui:
+ case AArch64::LDRWui:
+ case AArch64::LDRSWui:
+ // Unscaled instructions.
+ case AArch64::STURSi:
+ case AArch64::STURDi:
+ case AArch64::STURQi:
+ case AArch64::STURWi:
+ case AArch64::STURXi:
+ case AArch64::LDURSi:
+ case AArch64::LDURDi:
+ case AArch64::LDURQi:
+ case AArch64::LDURWi:
+ case AArch64::LDURXi:
+ case AArch64::LDURSWi:
+ return true;
+ }
+}
+
+unsigned AArch64InstrInfo::convertToFlagSettingOpc(unsigned Opc,
+ bool &Is64Bit) {
+ switch (Opc) {
+ default:
+ llvm_unreachable("Opcode has no flag setting equivalent!");
+ // 32-bit cases:
+ case AArch64::ADDWri:
+ Is64Bit = false;
+ return AArch64::ADDSWri;
+ case AArch64::ADDWrr:
+ Is64Bit = false;
+ return AArch64::ADDSWrr;
+ case AArch64::ADDWrs:
+ Is64Bit = false;
+ return AArch64::ADDSWrs;
+ case AArch64::ADDWrx:
+ Is64Bit = false;
+ return AArch64::ADDSWrx;
+ case AArch64::ANDWri:
+ Is64Bit = false;
+ return AArch64::ANDSWri;
+ case AArch64::ANDWrr:
+ Is64Bit = false;
+ return AArch64::ANDSWrr;
+ case AArch64::ANDWrs:
+ Is64Bit = false;
+ return AArch64::ANDSWrs;
+ case AArch64::BICWrr:
+ Is64Bit = false;
+ return AArch64::BICSWrr;
+ case AArch64::BICWrs:
+ Is64Bit = false;
+ return AArch64::BICSWrs;
+ case AArch64::SUBWri:
+ Is64Bit = false;
+ return AArch64::SUBSWri;
+ case AArch64::SUBWrr:
+ Is64Bit = false;
+ return AArch64::SUBSWrr;
+ case AArch64::SUBWrs:
+ Is64Bit = false;
+ return AArch64::SUBSWrs;
+ case AArch64::SUBWrx:
+ Is64Bit = false;
+ return AArch64::SUBSWrx;
+ // 64-bit cases:
+ case AArch64::ADDXri:
+ Is64Bit = true;
+ return AArch64::ADDSXri;
+ case AArch64::ADDXrr:
+ Is64Bit = true;
+ return AArch64::ADDSXrr;
+ case AArch64::ADDXrs:
+ Is64Bit = true;
+ return AArch64::ADDSXrs;
+ case AArch64::ADDXrx:
+ Is64Bit = true;
+ return AArch64::ADDSXrx;
+ case AArch64::ANDXri:
+ Is64Bit = true;
+ return AArch64::ANDSXri;
+ case AArch64::ANDXrr:
+ Is64Bit = true;
+ return AArch64::ANDSXrr;
+ case AArch64::ANDXrs:
+ Is64Bit = true;
+ return AArch64::ANDSXrs;
+ case AArch64::BICXrr:
+ Is64Bit = true;
+ return AArch64::BICSXrr;
+ case AArch64::BICXrs:
+ Is64Bit = true;
+ return AArch64::BICSXrs;
+ case AArch64::SUBXri:
+ Is64Bit = true;
+ return AArch64::SUBSXri;
+ case AArch64::SUBXrr:
+ Is64Bit = true;
+ return AArch64::SUBSXrr;
+ case AArch64::SUBXrs:
+ Is64Bit = true;
+ return AArch64::SUBSXrs;
+ case AArch64::SUBXrx:
+ Is64Bit = true;
+ return AArch64::SUBSXrx;
+ }
}
// Is this a candidate for ld/st merging or pairing? For example, we don't
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h?rev=324745&r1=324744&r2=324745&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h Fri Feb 9 08:14:41 2018
@@ -64,165 +64,51 @@ public:
/// Returns true if there is a shiftable register and that the shift value
/// is non-zero.
- bool hasShiftedReg(const MachineInstr &MI) const;
+ static bool hasShiftedReg(const MachineInstr &MI);
/// Returns true if there is an extendable register and that the extending
/// value is non-zero.
- bool hasExtendedReg(const MachineInstr &MI) const;
+ static bool hasExtendedReg(const MachineInstr &MI);
/// \brief Does this instruction set its full destination register to zero?
- bool isGPRZero(const MachineInstr &MI) const;
+ static bool isGPRZero(const MachineInstr &MI);
/// \brief Does this instruction rename a GPR without modifying bits?
- bool isGPRCopy(const MachineInstr &MI) const;
+ static bool isGPRCopy(const MachineInstr &MI);
/// \brief Does this instruction rename an FPR without modifying bits?
- bool isFPRCopy(const MachineInstr &MI) const;
+ static bool isFPRCopy(const MachineInstr &MI);
/// Return true if this is load/store scales or extends its register offset.
/// This refers to scaling a dynamic index as opposed to scaled immediates.
/// MI should be a memory op that allows scaled addressing.
- bool isScaledAddr(const MachineInstr &MI) const;
+ static bool isScaledAddr(const MachineInstr &MI);
/// Return true if pairing the given load or store is hinted to be
/// unprofitable.
- bool isLdStPairSuppressed(const MachineInstr &MI) const;
+ static bool isLdStPairSuppressed(const MachineInstr &MI);
/// Return true if the given load or store is a strided memory access.
- bool isStridedAccess(const MachineInstr &MI) const;
+ static bool isStridedAccess(const MachineInstr &MI);
/// Return true if this is an unscaled load/store.
- bool isUnscaledLdSt(unsigned Opc) const;
-
- /// Return true if this is an unscaled load/store.
- bool isUnscaledLdSt(MachineInstr &MI) const;
-
- static bool isPairableLdStInst(const MachineInstr &MI) {
- switch (MI.getOpcode()) {
- default:
- return false;
- // Scaled instructions.
- case AArch64::STRSui:
- case AArch64::STRDui:
- case AArch64::STRQui:
- case AArch64::STRXui:
- case AArch64::STRWui:
- case AArch64::LDRSui:
- case AArch64::LDRDui:
- case AArch64::LDRQui:
- case AArch64::LDRXui:
- case AArch64::LDRWui:
- case AArch64::LDRSWui:
- // Unscaled instructions.
- case AArch64::STURSi:
- case AArch64::STURDi:
- case AArch64::STURQi:
- case AArch64::STURWi:
- case AArch64::STURXi:
- case AArch64::LDURSi:
- case AArch64::LDURDi:
- case AArch64::LDURQi:
- case AArch64::LDURWi:
- case AArch64::LDURXi:
- case AArch64::LDURSWi:
- return true;
- }
+ static bool isUnscaledLdSt(unsigned Opc);
+ static bool isUnscaledLdSt(MachineInstr &MI) {
+ return isUnscaledLdSt(MI.getOpcode());
}
+ /// Return true if pairing the given load or store may be paired with another.
+ static bool isPairableLdStInst(const MachineInstr &MI);
+
/// \brief Return the opcode that set flags when possible. The caller is
/// responsible for ensuring the opc has a flag setting equivalent.
- static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit) {
- switch (Opc) {
- default:
- llvm_unreachable("Opcode has no flag setting equivalent!");
- // 32-bit cases:
- case AArch64::ADDWri:
- Is64Bit = false;
- return AArch64::ADDSWri;
- case AArch64::ADDWrr:
- Is64Bit = false;
- return AArch64::ADDSWrr;
- case AArch64::ADDWrs:
- Is64Bit = false;
- return AArch64::ADDSWrs;
- case AArch64::ADDWrx:
- Is64Bit = false;
- return AArch64::ADDSWrx;
- case AArch64::ANDWri:
- Is64Bit = false;
- return AArch64::ANDSWri;
- case AArch64::ANDWrr:
- Is64Bit = false;
- return AArch64::ANDSWrr;
- case AArch64::ANDWrs:
- Is64Bit = false;
- return AArch64::ANDSWrs;
- case AArch64::BICWrr:
- Is64Bit = false;
- return AArch64::BICSWrr;
- case AArch64::BICWrs:
- Is64Bit = false;
- return AArch64::BICSWrs;
- case AArch64::SUBWri:
- Is64Bit = false;
- return AArch64::SUBSWri;
- case AArch64::SUBWrr:
- Is64Bit = false;
- return AArch64::SUBSWrr;
- case AArch64::SUBWrs:
- Is64Bit = false;
- return AArch64::SUBSWrs;
- case AArch64::SUBWrx:
- Is64Bit = false;
- return AArch64::SUBSWrx;
- // 64-bit cases:
- case AArch64::ADDXri:
- Is64Bit = true;
- return AArch64::ADDSXri;
- case AArch64::ADDXrr:
- Is64Bit = true;
- return AArch64::ADDSXrr;
- case AArch64::ADDXrs:
- Is64Bit = true;
- return AArch64::ADDSXrs;
- case AArch64::ADDXrx:
- Is64Bit = true;
- return AArch64::ADDSXrx;
- case AArch64::ANDXri:
- Is64Bit = true;
- return AArch64::ANDSXri;
- case AArch64::ANDXrr:
- Is64Bit = true;
- return AArch64::ANDSXrr;
- case AArch64::ANDXrs:
- Is64Bit = true;
- return AArch64::ANDSXrs;
- case AArch64::BICXrr:
- Is64Bit = true;
- return AArch64::BICSXrr;
- case AArch64::BICXrs:
- Is64Bit = true;
- return AArch64::BICSXrs;
- case AArch64::SUBXri:
- Is64Bit = true;
- return AArch64::SUBSXri;
- case AArch64::SUBXrr:
- Is64Bit = true;
- return AArch64::SUBSXrr;
- case AArch64::SUBXrs:
- Is64Bit = true;
- return AArch64::SUBSXrs;
- case AArch64::SUBXrx:
- Is64Bit = true;
- return AArch64::SUBSXrx;
- }
- }
+ static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit);
/// Return true if this is a load/store that can be potentially paired/merged.
bool isCandidateToMergeOrPair(MachineInstr &MI) const;
/// Hint that pairing the given load or store is unprofitable.
- void suppressLdStPair(MachineInstr &MI) const;
+ static void suppressLdStPair(MachineInstr &MI);
bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
int64_t &Offset,
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