[PATCH] D43014: [X86][SSE] Enable SMIN/SMAX/UMIN/UMAX custom lowering for all legal types

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:22023
+  // using the SMIN/SMAX instructions and flipping the signbit back.
+  if (VT == MVT::v8i16) {
+    assert((Opcode == ISD::UMIN || Opcode == ISD::UMAX) &&
----------------
What if we can prove the sign bit is 0? Or do we already do that in some DAG combine?


Repository:
  rL LLVM

https://reviews.llvm.org/D43014