[llvm] r324696 - [GISel]: Verify COPIES involving generic registers.
Aditya Nandakumar via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 8 17:27:23 PST 2018
Author: aditya_nandakumar
Date: Thu Feb 8 17:27:23 2018
New Revision: 324696
URL: http://llvm.org/viewvc/llvm-project?rev=324696&view=rev
Log:
[GISel]: Verify COPIES involving generic registers.
Add verification for copies involving generic registers if they are
compatible - ie if it is a generic copy, then the types are the
same, and if a COPY b/w generic and target virtual register, then
the sizes should be the same. Only checks if there are no sub registers
involved for now.
https://reviews.llvm.org/D37775
Added:
llvm/trunk/test/Verifier/test_copy.mir
llvm/trunk/test/Verifier/test_copy_mismatch_types.mir
Modified:
llvm/trunk/lib/CodeGen/MachineVerifier.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
llvm/trunk/test/CodeGen/MIR/AArch64/intrinsics.mir
llvm/trunk/test/CodeGen/MIR/AMDGPU/intrinsics.mir
Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=324696&r1=324695&r2=324696&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Thu Feb 8 17:27:23 2018
@@ -971,6 +971,36 @@ void MachineVerifier::visitMachineInstrB
MI);
break;
}
+ case TargetOpcode::COPY: {
+ if (foundErrors)
+ break;
+ const MachineOperand &DstOp = MI->getOperand(0);
+ const MachineOperand &SrcOp = MI->getOperand(1);
+ LLT DstTy = MRI->getType(DstOp.getReg());
+ LLT SrcTy = MRI->getType(SrcOp.getReg());
+ if (SrcTy.isValid() && DstTy.isValid()) {
+ // If both types are valid, check that the types are the same.
+ if (SrcTy != DstTy) {
+ report("Copy Instruction is illegal with mismatching types", MI);
+ errs() << "Def = " << DstTy << ", Src = " << SrcTy << "\n";
+ }
+ }
+ if (SrcTy.isValid() || DstTy.isValid()) {
+ // If one of them have valid types, let's just check they have the same
+ // size.
+ unsigned SrcSize = TRI->getRegSizeInBits(SrcOp.getReg(), *MRI);
+ unsigned DstSize = TRI->getRegSizeInBits(DstOp.getReg(), *MRI);
+ assert(SrcSize && "Expecting size here");
+ assert(DstSize && "Expecting size here");
+ if (SrcSize != DstSize)
+ if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
+ report("Copy Instruction is illegal with mismatching sizes", MI);
+ errs() << "Def Size = " << DstSize << ", Src Size = " << SrcSize
+ << "\n";
+ }
+ }
+ break;
+ }
case TargetOpcode::STATEPOINT:
if (!MI->getOperand(StatepointOpers::IDPos).isImm() ||
!MI->getOperand(StatepointOpers::NBytesPos).isImm() ||
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir?rev=324696&r1=324695&r2=324696&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir Thu Feb 8 17:27:23 2018
@@ -68,7 +68,7 @@ body: |
%1:_(s128) = G_MERGE_VALUES %0, %0
%2:_(s64) = G_EXTRACT %1, 0
%3:_(s64) = G_ADD %2, %2
- $w0 = COPY %3
+ $x0 = COPY %3
...
---
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir?rev=324696&r1=324695&r2=324696&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fptoi.mir Thu Feb 8 17:27:23 2018
@@ -147,11 +147,12 @@ body: |
; CHECK-LABEL: name: test_fptosi_s1_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[FPTOSI]](s32)
- ; CHECK: $x0 = COPY [[TRUNC]](s1)
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[FPTOSI]](s32)
+ ; CHECK: $x0 = COPY [[ANYEXT]](s64)
%0:_(s32) = COPY $w0
%1:_(s1) = G_FPTOSI %0
- $x0 = COPY %1
+ %2:_(s64) = G_ANYEXT %1
+ $x0 = COPY %2
...
---
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir?rev=324696&r1=324695&r2=324696&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir Thu Feb 8 17:27:23 2018
@@ -87,7 +87,7 @@ body: |
; CHECK: [[SITOFP:%[0-9]+]]:_(s64) = G_SITOFP [[COPY]](s32)
%0:_(s32) = COPY $w0
%1:_(s64) = G_SITOFP %0
- $w0 = COPY %1
+ $x0 = COPY %1
...
---
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir?rev=324696&r1=324695&r2=324696&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-or.mir Thu Feb 8 17:27:23 2018
@@ -12,14 +12,15 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[TRUNC]], [[TRUNC1]]
- ; CHECK: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[OR]](s32)
- ; CHECK: $x0 = COPY [[TRUNC2]](s8)
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32)
+ ; CHECK: $x0 = COPY [[ANYEXT]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s8) = G_TRUNC %0
%3:_(s8) = G_TRUNC %1
%4:_(s8) = G_OR %2, %3
- $x0 = COPY %4
+ %5:_(s64) = G_ANYEXT %4
+ $x0 = COPY %5
...
---
Modified: llvm/trunk/test/CodeGen/MIR/AArch64/intrinsics.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AArch64/intrinsics.mir?rev=324696&r1=324695&r2=324696&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/intrinsics.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AArch64/intrinsics.mir Thu Feb 8 17:27:23 2018
@@ -9,10 +9,10 @@
...
---
# Completely invalid code, but it checks that intrinsics round-trip properly.
-# CHECK: $x0 = COPY intrinsic(@llvm.returnaddress)
+# CHECK: G_INTRINSIC intrinsic(@llvm.returnaddress)
name: use_intrin
body: |
bb.0:
- $x0 = COPY intrinsic(@llvm.returnaddress)
+ %0:_(s64) = G_INTRINSIC intrinsic(@llvm.returnaddress)
RET_ReallyLR
...
Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/intrinsics.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/intrinsics.mir?rev=324696&r1=324695&r2=324696&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/intrinsics.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/intrinsics.mir Thu Feb 8 17:27:23 2018
@@ -16,6 +16,6 @@ registers:
body: |
bb.0:
; CHECK-LABEL: name: use_intrin
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY intrinsic(@llvm.amdgcn.sbfe)
- %0(s64) = COPY intrinsic(@llvm.amdgcn.sbfe.i32)
+ ; CHECK: %0:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sbfe)
+ %0(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sbfe.i32)
...
Added: llvm/trunk/test/Verifier/test_copy.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Verifier/test_copy.mir?rev=324696&view=auto
==============================================================================
--- llvm/trunk/test/Verifier/test_copy.mir (added)
+++ llvm/trunk/test/Verifier/test_copy.mir Thu Feb 8 17:27:23 2018
@@ -0,0 +1,33 @@
+#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: global-isel, aarch64-registered-target
+--- |
+ ; ModuleID = 'test.ll'
+ source_filename = "test.ll"
+ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+ target triple = "aarch64-unknown-unknown"
+
+ define i32 @test_copy(i32 %argc) {
+ ret i32 0
+ }
+ define i32 @test_copy_type_mismatch(i32 %argc) {
+ ret i32 0
+ }
+
+...
+---
+name: test_copy
+legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+liveins:
+body: |
+ bb.0:
+ liveins: $w0
+ ; This test is used to catch verifier errors with copys having mismatching sizes
+ ; CHECK: Bad machine code: Copy Instruction is illegal with mismatching sizes
+
+ %0(s8) = COPY $w0
+...
Added: llvm/trunk/test/Verifier/test_copy_mismatch_types.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Verifier/test_copy_mismatch_types.mir?rev=324696&view=auto
==============================================================================
--- llvm/trunk/test/Verifier/test_copy_mismatch_types.mir (added)
+++ llvm/trunk/test/Verifier/test_copy_mismatch_types.mir Thu Feb 8 17:27:23 2018
@@ -0,0 +1,31 @@
+#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: global-isel, aarch64-registered-target
+--- |
+ ; ModuleID = 'test.ll'
+ source_filename = "test.ll"
+ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+ target triple = "aarch64-unknown-unknown"
+
+ define i32 @test_copy(i32 %argc) {
+ ret i32 0
+ }
+
+...
+---
+name: test_copy
+legalized: true
+regBankSelected: false
+selected: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+liveins:
+body: |
+ bb.0:
+ liveins: $w0
+ ; This test is used to catch verifier errors with copys having mismatching sizes
+ ; CHECK: Bad machine code: Copy Instruction is illegal with mismatching types
+
+ %0(s32) = COPY $w0
+ %1:_(<2 x s16>) = COPY %0
+...
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