[PATCH] D43042: [MachineOperand][Target] Add target option to disable setting MachineOperand::isRenamable

[escha via Phabricator via llvm-commits]

escha added a comment.

This looks like it might fix the problem we've been having, but i'm still extremely nervous about the overall concept. this feels like a fantastically large amount of machinery for such a small optimization, including this dubiously defined "isRenamable" flag that applies to operand registers even though renamability seems to be more of a property of the instruction.

Furthermore, the fact that vregs are always renamable means it's impossible to pass down the "renamability" of a register from before register allocation: we couldn't even use this feature if we wanted to.

I'm not going to hold it up, but all of this feels like a very roundabout approach to me.


Repository:
  rL LLVM

https://reviews.llvm.org/D43042