[llvm] r324637 - [X86] Add shift undef, %X tests

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Thu Feb  8 11:20:34 2018
New Revision: 324637

URL: http://llvm.org/viewvc/llvm-project?rev=324637&view=rev
Log:
[X86] Add shift undef, %X tests

Modified:
    llvm/trunk/test/CodeGen/X86/combine-shl.ll
    llvm/trunk/test/CodeGen/X86/combine-sra.ll
    llvm/trunk/test/CodeGen/X86/combine-srl.ll

Modified: llvm/trunk/test/CodeGen/X86/combine-shl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-shl.ll?rev=324637&r1=324636&r2=324637&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-shl.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-shl.ll Thu Feb  8 11:20:34 2018
@@ -3,6 +3,33 @@
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX-SLOW
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-shuffle | FileCheck %s --check-prefixes=AVX,AVX-FAST
 
+; fold (shl undef, x) -> 0
+define i32 @combine_shl_undef0(i32 %x) {
+; SSE-LABEL: combine_shl_undef0:
+; SSE:       # %bb.0:
+; SSE-NEXT:    xorl %eax, %eax
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: combine_shl_undef0:
+; AVX:       # %bb.0:
+; AVX-NEXT:    xorl %eax, %eax
+; AVX-NEXT:    retq
+  %1 = shl i32 undef, %x
+  ret i32 %1
+}
+
+define <4 x i32> @combine_vec_shl_undef0(<4 x i32> %x) {
+; SSE-LABEL: combine_vec_shl_undef0:
+; SSE:       # %bb.0:
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: combine_vec_shl_undef0:
+; AVX:       # %bb.0:
+; AVX-NEXT:    retq
+  %1 = shl <4 x i32> undef, %x
+  ret <4 x i32> %1
+}
+
 ; fold (shl 0, x) -> 0
 define <4 x i32> @combine_vec_shl_zero(<4 x i32> %x) {
 ; SSE-LABEL: combine_vec_shl_zero:

Modified: llvm/trunk/test/CodeGen/X86/combine-sra.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-sra.ll?rev=324637&r1=324636&r2=324637&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-sra.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-sra.ll Thu Feb  8 11:20:34 2018
@@ -3,6 +3,31 @@
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2-SLOW
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-shuffle | FileCheck %s --check-prefixes=AVX,AVX2-FAST
 
+; fold (sra undef, x) -> undef
+define i32 @combine_lshr_undef0(i32 %x) {
+; SSE-LABEL: combine_lshr_undef0:
+; SSE:       # %bb.0:
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: combine_lshr_undef0:
+; AVX:       # %bb.0:
+; AVX-NEXT:    retq
+  %1 = ashr i32 undef, %x
+  ret i32 %1
+}
+
+define <4 x i32> @combine_vec_ashr_undef0(<4 x i32> %x) {
+; SSE-LABEL: combine_vec_ashr_undef0:
+; SSE:       # %bb.0:
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: combine_vec_ashr_undef0:
+; AVX:       # %bb.0:
+; AVX-NEXT:    retq
+  %1 = ashr <4 x i32> undef, %x
+  ret <4 x i32> %1
+}
+
 ; fold (sra 0, x) -> 0
 define <4 x i32> @combine_vec_ashr_zero(<4 x i32> %x) {
 ; SSE-LABEL: combine_vec_ashr_zero:

Modified: llvm/trunk/test/CodeGen/X86/combine-srl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-srl.ll?rev=324637&r1=324636&r2=324637&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-srl.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-srl.ll Thu Feb  8 11:20:34 2018
@@ -3,6 +3,33 @@
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2-SLOW
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+fast-variable-shuffle | FileCheck %s --check-prefixes=AVX,AVX2-FAST
 
+; fold (srl undef, x) -> 0
+define i32 @combine_lshr_undef0(i32 %x) {
+; SSE-LABEL: combine_lshr_undef0:
+; SSE:       # %bb.0:
+; SSE-NEXT:    xorl %eax, %eax
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: combine_lshr_undef0:
+; AVX:       # %bb.0:
+; AVX-NEXT:    xorl %eax, %eax
+; AVX-NEXT:    retq
+  %1 = lshr i32 undef, %x
+  ret i32 %1
+}
+
+define <4 x i32> @combine_vec_lshr_undef0(<4 x i32> %x) {
+; SSE-LABEL: combine_vec_lshr_undef0:
+; SSE:       # %bb.0:
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: combine_vec_lshr_undef0:
+; AVX:       # %bb.0:
+; AVX-NEXT:    retq
+  %1 = lshr <4 x i32> undef, %x
+  ret <4 x i32> %1
+}
+
 ; fold (srl 0, x) -> 0
 define <4 x i32> @combine_vec_lshr_zero(<4 x i32> %x) {
 ; SSE-LABEL: combine_vec_lshr_zero: