[llvm] r324629 - [InstCombine] Add vector urem tests.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Thu Feb  8 10:10:08 2018
New Revision: 324629

URL: http://llvm.org/viewvc/llvm-project?rev=324629&view=rev
Log:
[InstCombine] Add vector urem tests.

Improve coverage of InstCombiner::visitURem for vector types

Modified:
    llvm/trunk/test/Transforms/InstCombine/vector-urem.ll

Modified: llvm/trunk/test/Transforms/InstCombine/vector-urem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/vector-urem.ll?rev=324629&r1=324628&r2=324629&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/vector-urem.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/vector-urem.ll Thu Feb  8 10:10:08 2018
@@ -19,3 +19,57 @@ define <4 x i32> @test_v4i32_const_pow2(
   ret <4 x i32> %1
 }
 
+define <4 x i32> @test_v4i32_const_pow2_undef(<4 x i32> %a0) {
+; CHECK-LABEL: @test_v4i32_const_pow2_undef(
+; CHECK-NEXT:    ret <4 x i32> undef
+;
+  %1 = urem <4 x i32> %a0, <i32 1, i32 2, i32 4, i32 undef>
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @test_v4i32_one(<4 x i32> %a0) {
+; CHECK-LABEL: @test_v4i32_one(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ne <4 x i32> [[A0:%.*]], <i32 1, i32 1, i32 1, i32 1>
+; CHECK-NEXT:    [[TMP2:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32>
+; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+;
+  %1 = urem <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %a0
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @test_v4i32_one_undef(<4 x i32> %a0) {
+; CHECK-LABEL: @test_v4i32_one_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = urem <4 x i32> <i32 1, i32 1, i32 1, i32 undef>, [[A0:%.*]]
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = urem <4 x i32> <i32 1, i32 1, i32 1, i32 undef>, %a0
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @test_v4i32_negconstsplat(<4 x i32> %a0) {
+; CHECK-LABEL: @test_v4i32_negconstsplat(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult <4 x i32> [[A0:%.*]], <i32 -3, i32 -3, i32 -3, i32 -3>
+; CHECK-NEXT:    [[TMP2:%.*]] = add <4 x i32> [[A0]], <i32 3, i32 3, i32 3, i32 3>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[A0]], <4 x i32> [[TMP2]]
+; CHECK-NEXT:    ret <4 x i32> [[TMP3]]
+;
+  %1 = urem <4 x i32> %a0, <i32 -3, i32 -3, i32 -3, i32 -3>
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @test_v4i32_negconst(<4 x i32> %a0) {
+; CHECK-LABEL: @test_v4i32_negconst(
+; CHECK-NEXT:    [[TMP1:%.*]] = urem <4 x i32> [[A0:%.*]], <i32 -3, i32 -5, i32 -7, i32 -9>
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = urem <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 -9>
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @test_v4i32_negconst_undef(<4 x i32> %a0) {
+; CHECK-LABEL: @test_v4i32_negconst_undef(
+; CHECK-NEXT:    ret <4 x i32> undef
+;
+  %1 = urem <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 undef>
+  ret <4 x i32> %1
+}