[llvm] r324600 - [ARM] Fix disassembly of invalid banked register moves

[Oliver Stannard via llvm-commits]

Author: olista01
Date: Thu Feb  8 05:06:08 2018
New Revision: 324600

URL: http://llvm.org/viewvc/llvm-project?rev=324600&view=rev
Log:
[ARM] Fix disassembly of invalid banked register moves

When disassembling banked register move instructions, we don't have an
assembly syntax for the unallocated register numbers, so we have to
return Fail rather than SoftFail. Previously we were returning SoftFail,
then crashing in the InstPrinter as we have no way to represent these
encodings in an assembly string.

This also switches the decoder to use the table-generated list of banked
registers, removing the duplicated list of encodings.

Differential revision: https://reviews.llvm.org/D43066


Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM/invalid-armv7.txt
    llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=324600&r1=324599&r2=324600&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Thu Feb  8 05:06:08 2018
@@ -4205,15 +4205,8 @@ static DecodeStatus DecodeBankedReg(MCIn
   // The table of encodings for these banked registers comes from B9.2.3 of the
   // ARM ARM. There are patterns, but nothing regular enough to make this logic
   // neater. So by fiat, these values are UNPREDICTABLE:
-  if (!R) {
-    if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
-        SysM == 0x1a || SysM == 0x1b)
-      return MCDisassembler::SoftFail;
-  } else {
-    if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
-        SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
-      return MCDisassembler::SoftFail;
-  }
+  if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM))
+    return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createImm(Val));
   return MCDisassembler::Success;

Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-armv7.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-armv7.txt?rev=324600&r1=324599&r2=324600&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-armv7.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-armv7.txt Thu Feb  8 05:06:08 2018
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple armv7 2>&1 | FileCheck %s
+# RUN: not llvm-mc -disassemble %s -mcpu cortex-a15 -triple armv7 2>&1 | FileCheck %s
 
 # This file is checking ARMv7 encodings which are globally invalid, usually due
 # to the constraints of the instructions not being met. For example invalid
@@ -500,3 +500,19 @@
 [0x3d 0x3c 0xa0 0xf4]
 # CHECK: invalid instruction encoding
 # CHECK-NEXT: [0x3d 0x3c 0xa0 0xf4]
+
+
+#------------------------------------------------------------------------------
+# Undefined encodings for MSR/MRS (banked register)
+#------------------------------------------------------------------------------
+# These have a banked register encoding of 0b111111, which is unallocated.
+
+# msr <invalid>, r0
+[0x00,0xf3,0x6f,0xe1]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x00,0xf3,0x6f,0xe1]
+
+# mrs r0, <invalid>
+[0x00,0x03,0x4f,0xe1]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x00,0x03,0x4f,0xe1]

Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7.txt?rev=324600&r1=324599&r2=324600&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7.txt Thu Feb  8 05:06:08 2018
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple thumbv7 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V7
+# RUN: not llvm-mc -disassemble %s -mcpu cortex-a15 -triple thumbv7 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V7
 # RUN: not llvm-mc -disassemble %s -mcpu cortex-a53 -triple thumbv8 2>&1 | FileCheck %s
 
 # This file is checking Thumbv7 encodings which are globally invalid, usually due
@@ -379,3 +379,18 @@
 [0x63 0xeb 0x2d 0x46]
 # CHECK-V7: warning: potentially undefined instruction encoding
 # CHECK-V7-NEXT: [0x63 0xeb 0x2d 0x46]
+
+#------------------------------------------------------------------------------
+# Undefined encodings for MSR/MRS (banked register)
+#------------------------------------------------------------------------------
+# These have a banked register encoding of 0b111111, which is unallocated.
+
+# msr <invalid>, r0
+[0x90,0xf3,0x30,0x8f]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0x90,0xf3,0x30,0x8f]
+
+# mrs r0, <invalid>
+[0xff,0xf3,0x30,0x80]
+# CHECK: invalid instruction encoding
+# CHECK-NEXT: [0xff,0xf3,0x30,0x80]