[llvm] r324583 - [AVR] Fix the testsuite after '%' changed to '$' in MIR
Dylan McKay via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 8 01:17:11 PST 2018
Author: dylanmckay
Date: Thu Feb 8 01:17:11 2018
New Revision: 324583
URL: http://llvm.org/viewvc/llvm-project?rev=324583&view=rev
Log:
[AVR] Fix the testsuite after '%' changed to '$' in MIR
Modified:
llvm/trunk/test/CodeGen/AVR/pseudo/ADCWRdRr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/ADDWRdRr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/ANDIWRdK.mir
llvm/trunk/test/CodeGen/AVR/pseudo/ANDWRdRr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/ASRWRd.mir
llvm/trunk/test/CodeGen/AVR/pseudo/COMWRd.mir
llvm/trunk/test/CodeGen/AVR/pseudo/CPCWRdRr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/CPWRdRr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/EORWRdRr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/FRMIDX.mir
llvm/trunk/test/CodeGen/AVR/pseudo/INWRdA.mir
llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ-same-src-dst.mir
llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir
llvm/trunk/test/CodeGen/AVR/pseudo/LDIWRdK.mir
llvm/trunk/test/CodeGen/AVR/pseudo/LDSWRdK.mir
llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir
llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir
llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir
llvm/trunk/test/CodeGen/AVR/pseudo/LSLWRd.mir
llvm/trunk/test/CodeGen/AVR/pseudo/LSRWRd.mir
llvm/trunk/test/CodeGen/AVR/pseudo/ORIWRdK.mir
llvm/trunk/test/CodeGen/AVR/pseudo/ORWRdRr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/OUTWARr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/POPWRd.mir
llvm/trunk/test/CodeGen/AVR/pseudo/PUSHWRr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/SBCIWRdK.mir
llvm/trunk/test/CodeGen/AVR/pseudo/SBCWRdRr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/SEXT.mir
llvm/trunk/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/STSWKRr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrRr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/SUBIWRdK.mir
llvm/trunk/test/CodeGen/AVR/pseudo/SUBWRdRr.mir
llvm/trunk/test/CodeGen/AVR/pseudo/ZEXT.mir
llvm/trunk/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
llvm/trunk/test/CodeGen/AVR/select-must-add-unconditional-jump.ll
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/ADCWRdRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/ADCWRdRr.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/ADCWRdRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/ADCWRdRr.mir Thu Feb 8 01:17:11 2018
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_adcwrdrr
- ; CHECK: %r14 = ADCRdRr %r14, %r20, implicit-def %sreg, implicit %sreg
- ; CHECK-LABEL: %r15 = ADCRdRr %r15, %r21, implicit-def %sreg, implicit killed %sreg
+ ; CHECK: $r14 = ADCRdRr $r14, $r20, implicit-def $sreg, implicit $sreg
+ ; CHECK-LABEL: $r15 = ADCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
- %r15r14 = ADCWRdRr %r15r14, %r21r20, implicit-def %sreg, implicit %sreg
+ $r15r14 = ADCWRdRr $r15r14, $r21r20, implicit-def $sreg, implicit $sreg
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/ADDWRdRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/ADDWRdRr.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/ADDWRdRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/ADDWRdRr.mir Thu Feb 8 01:17:11 2018
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_addwrdrr
- ; CHECK: %r14 = ADDRdRr %r14, %r20, implicit-def %sreg
- ; CHECK-LABEL: %r15 = ADCRdRr %r15, %r21, implicit-def %sreg, implicit killed %sreg
+ ; CHECK: $r14 = ADDRdRr $r14, $r20, implicit-def $sreg
+ ; CHECK-LABEL: $r15 = ADCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
- %r15r14 = ADDWRdRr %r15r14, %r21r20, implicit-def %sreg
+ $r15r14 = ADDWRdRr $r15r14, $r21r20, implicit-def $sreg
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/ANDIWRdK.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/ANDIWRdK.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/ANDIWRdK.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/ANDIWRdK.mir Thu Feb 8 01:17:11 2018
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_andiwrdrr
- ; CHECK: %r16 = ANDIRdK %r16, 175, implicit-def dead %sreg
- ; CHECK-NEXT: %r17 = ANDIRdK %r17, 250, implicit-def %sreg
+ ; CHECK: $r16 = ANDIRdK $r16, 175, implicit-def dead $sreg
+ ; CHECK-NEXT: $r17 = ANDIRdK $r17, 250, implicit-def $sreg
- %r17r16 = ANDIWRdK %r17r16, 64175, implicit-def %sreg
+ $r17r16 = ANDIWRdK $r17r16, 64175, implicit-def $sreg
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/ANDWRdRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/ANDWRdRr.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/ANDWRdRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/ANDWRdRr.mir Thu Feb 8 01:17:11 2018
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_andwrdrr
- ; CHECK: %r14 = ANDRdRr %r14, %r20, implicit-def dead %sreg
- ; CHECK-NEXT: %r15 = ANDRdRr %r15, %r21, implicit-def %sreg
+ ; CHECK: $r14 = ANDRdRr $r14, $r20, implicit-def dead $sreg
+ ; CHECK-NEXT: $r15 = ANDRdRr $r15, $r21, implicit-def $sreg
- %r15r14 = ANDWRdRr %r15r14, %r21r20, implicit-def %sreg
+ $r15r14 = ANDWRdRr $r15r14, $r21r20, implicit-def $sreg
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/ASRWRd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/ASRWRd.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/ASRWRd.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/ASRWRd.mir Thu Feb 8 01:17:11 2018
@@ -15,8 +15,8 @@ body: |
; CHECK-LABEL: test
- ; CHECK: %r15 = ASRRd %r15, implicit-def %sreg
- ; CHECK-NEXT: %r14 = RORRd %r14, implicit-def %sreg, implicit killed %sreg
+ ; CHECK: $r15 = ASRRd $r15, implicit-def $sreg
+ ; CHECK-NEXT: $r14 = RORRd $r14, implicit-def $sreg, implicit killed $sreg
- %r15r14 = ASRWRd %r15r14, implicit-def %sreg
+ $r15r14 = ASRWRd $r15r14, implicit-def $sreg
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/COMWRd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/COMWRd.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/COMWRd.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/COMWRd.mir Thu Feb 8 01:17:11 2018
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_comwrd
- ; CHECK: %r14 = COMRd %r14, implicit-def dead %sreg
- ; CHECK-NEXT: %r15 = COMRd %r15, implicit-def %sreg
+ ; CHECK: $r14 = COMRd $r14, implicit-def dead $sreg
+ ; CHECK-NEXT: $r15 = COMRd $r15, implicit-def $sreg
- %r15r14 = COMWRd %r15r14, implicit-def %sreg
+ $r15r14 = COMWRd $r15r14, implicit-def $sreg
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/CPCWRdRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/CPCWRdRr.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/CPCWRdRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/CPCWRdRr.mir Thu Feb 8 01:17:11 2018
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_cpcwrdrr
- ; CHECK: CPCRdRr %r20, %r22, implicit-def %sreg, implicit killed %sreg
- ; CHECK-NEXT: CPCRdRr %r21, %r23, implicit-def %sreg, implicit killed %sreg
+ ; CHECK: CPCRdRr $r20, $r22, implicit-def $sreg, implicit killed $sreg
+ ; CHECK-NEXT: CPCRdRr $r21, $r23, implicit-def $sreg, implicit killed $sreg
- CPCWRdRr %r21r20, %r23r22, implicit-def %sreg, implicit %sreg
+ CPCWRdRr $r21r20, $r23r22, implicit-def $sreg, implicit $sreg
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/CPWRdRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/CPWRdRr.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/CPWRdRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/CPWRdRr.mir Thu Feb 8 01:17:11 2018
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_cpwrdrr
- ; CHECK: CPRdRr %r14, %r20, implicit-def %sreg
- ; CHECK-NEXT: CPCRdRr %r15, %r21, implicit-def %sreg, implicit killed %sreg
+ ; CHECK: CPRdRr $r14, $r20, implicit-def $sreg
+ ; CHECK-NEXT: CPCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
- CPWRdRr %r15r14, %r21r20, implicit-def %sreg
+ CPWRdRr $r15r14, $r21r20, implicit-def $sreg
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/EORWRdRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/EORWRdRr.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/EORWRdRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/EORWRdRr.mir Thu Feb 8 01:17:11 2018
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_eorwrdrr
- ; CHECK: %r14 = EORRdRr %r14, %r20, implicit-def dead %sreg
- ; CHECK-NEXT: %r15 = EORRdRr %r15, %r21, implicit-def %sreg
+ ; CHECK: $r14 = EORRdRr $r14, $r20, implicit-def dead $sreg
+ ; CHECK-NEXT: $r15 = EORRdRr $r15, $r21, implicit-def $sreg
- %r15r14 = EORWRdRr %r15r14, %r21r20, implicit-def %sreg
+ $r15r14 = EORWRdRr $r15r14, $r21r20, implicit-def $sreg
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/FRMIDX.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/FRMIDX.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/FRMIDX.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/FRMIDX.mir Thu Feb 8 01:17:11 2018
@@ -21,5 +21,5 @@ body: |
; CHECK-LABEL: test
- %r29r28 = FRMIDX %r31r30, 0, implicit-def %sreg
+ $r29r28 = FRMIDX $r31r30, 0, implicit-def $sreg
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/INWRdA.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/INWRdA.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/INWRdA.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/INWRdA.mir Thu Feb 8 01:17:11 2018
@@ -15,8 +15,8 @@ body: |
; CHECK-LABEL: test
- ; CHECK: %r14 = INRdA 31
- ; CHECK-NEXT: %r15 = INRdA 32
+ ; CHECK: $r14 = INRdA 31
+ ; CHECK-NEXT: $r15 = INRdA 32
- %r15r14 = INWRdA 31
+ $r15r14 = INWRdA 31
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ-same-src-dst.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ-same-src-dst.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ-same-src-dst.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ-same-src-dst.mir Thu Feb 8 01:17:11 2018
@@ -31,5 +31,5 @@ body: |
; CHECK-NEXT: mov r31, [[SCRATCH]]
; CHECK-NEXT: pop r30
- early-clobber %r31r30 = LDDWRdPtrQ undef %r31r30, 10
+ early-clobber $r31r30 = LDDWRdPtrQ undef $r31r30, 10
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir Thu Feb 8 01:17:11 2018
@@ -21,5 +21,5 @@ body: |
; CHECK: ldd r30, Y+10
; CHECK-NEXT: ldd r31, Y+11
- early-clobber %r31r30 = LDDWRdPtrQ undef %r29r28, 10
+ early-clobber $r31r30 = LDDWRdPtrQ undef $r29r28, 10
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir Thu Feb 8 01:17:11 2018
@@ -21,5 +21,5 @@ body: |
; CHECK: ldd r30, Y+1
; CHECK-NEXT: ldd r31, Y+2
- early-clobber %r31r30 = LDDWRdYQ undef %r29r28, 1
+ early-clobber $r31r30 = LDDWRdYQ undef $r29r28, 1
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LDIWRdK.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDIWRdK.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDIWRdK.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDIWRdK.mir Thu Feb 8 01:17:11 2018
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_ldiwrdrr
- ; CHECK: %r30 = LDIRdK 255
- ; CHECK-NEXT: %r31 = LDIRdK 9
+ ; CHECK: $r30 = LDIRdK 255
+ ; CHECK-NEXT: $r31 = LDIRdK 9
- %r31r30 = LDIWRdK 2559
+ $r31r30 = LDIWRdK 2559
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LDSWRdK.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDSWRdK.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDSWRdK.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDSWRdK.mir Thu Feb 8 01:17:11 2018
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_ldswrdrr
- ; CHECK: %r30 = LDSRdK 2559
- ; CHECK-NEXT: %r31 = LDSRdK 2560
+ ; CHECK: $r30 = LDSRdK 2559
+ ; CHECK-NEXT: $r31 = LDSRdK 2560
- %r31r30 = LDSWRdK 2559
+ $r31r30 = LDSWRdK 2559
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr-same-src-dst.mir Thu Feb 8 01:17:11 2018
@@ -24,6 +24,6 @@ body: |
; CHECK-NEXT: mov r31, [[SCRATCH]]
; CHECK-NEXT: pop r30
- early-clobber %r31r30 = LDWRdPtr undef %r31r30
+ early-clobber $r31r30 = LDWRdPtr undef $r31r30
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtr.mir Thu Feb 8 01:17:11 2018
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_ldwrdptr
- ; CHECK: %r0, %r31r30 = LDRdPtrPi %r31r30
- ; CHECK-NEXT: %r1 = LDRdPtr %r31r30
+ ; CHECK: $r0, $r31r30 = LDRdPtrPi $r31r30
+ ; CHECK-NEXT: $r1 = LDRdPtr $r31r30
- %r1r0 = LDWRdPtr %r31r30
+ $r1r0 = LDWRdPtr $r31r30
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPd.mir Thu Feb 8 01:17:11 2018
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_ldwrdptrpd
- ; CHECK: early-clobber %r1, %r31r30 = LDRdPtrPd killed %r31r30
- ; CHECK-NEXT: early-clobber %r0, %r31r30 = LDRdPtrPd killed %r31r30
+ ; CHECK: early-clobber $r1, $r31r30 = LDRdPtrPd killed $r31r30
+ ; CHECK-NEXT: early-clobber $r0, $r31r30 = LDRdPtrPd killed $r31r30
- %r1r0, %r31r30 = LDWRdPtrPd %r31r30
+ $r1r0, $r31r30 = LDWRdPtrPd $r31r30
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LDWRdPtrPi.mir Thu Feb 8 01:17:11 2018
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_ldwrdptrpi
- ; CHECK: early-clobber %r0, %r31r30 = LDRdPtrPi killed %r31r30
- ; CHECK-NEXT: early-clobber %r1, %r31r30 = LDRdPtrPi killed %r31r30
+ ; CHECK: early-clobber $r0, $r31r30 = LDRdPtrPi killed $r31r30
+ ; CHECK-NEXT: early-clobber $r1, $r31r30 = LDRdPtrPi killed $r31r30
- %r1r0, %r31r30 = LDWRdPtrPi %r31r30
+ $r1r0, $r31r30 = LDWRdPtrPi $r31r30
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LSLWRd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LSLWRd.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LSLWRd.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LSLWRd.mir Thu Feb 8 01:17:11 2018
@@ -15,8 +15,8 @@ body: |
; CHECK-LABEL: test
- ; CHECK: %r14 = LSLRd %r14, implicit-def %sreg
- ; CHECK-NEXT: %r15 = ROLRd %r15, implicit-def %sreg, implicit killed %sreg
+ ; CHECK: $r14 = LSLRd $r14, implicit-def $sreg
+ ; CHECK-NEXT: $r15 = ROLRd $r15, implicit-def $sreg, implicit killed $sreg
- %r15r14 = LSLWRd %r15r14, implicit-def %sreg
+ $r15r14 = LSLWRd $r15r14, implicit-def $sreg
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LSRWRd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LSRWRd.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LSRWRd.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LSRWRd.mir Thu Feb 8 01:17:11 2018
@@ -15,8 +15,8 @@ body: |
; CHECK-LABEL: test
- ; CHECK: %r15 = LSRRd %r15, implicit-def %sreg
- ; CHECK-NEXT: %r14 = RORRd %r14, implicit-def %sreg, implicit killed %sreg
+ ; CHECK: $r15 = LSRRd $r15, implicit-def $sreg
+ ; CHECK-NEXT: $r14 = RORRd $r14, implicit-def $sreg, implicit killed $sreg
- %r15r14 = LSRWRd %r15r14, implicit-def %sreg
+ $r15r14 = LSRWRd $r15r14, implicit-def $sreg
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/ORIWRdK.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/ORIWRdK.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/ORIWRdK.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/ORIWRdK.mir Thu Feb 8 01:17:11 2018
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_oriwrdrr
- ; CHECK: %r20 = ORIRdK %r20, 175, implicit-def dead %sreg
- ; CHECK-NEXT: %r21 = ORIRdK %r21, 250, implicit-def %sreg
+ ; CHECK: $r20 = ORIRdK $r20, 175, implicit-def dead $sreg
+ ; CHECK-NEXT: $r21 = ORIRdK $r21, 250, implicit-def $sreg
- %r21r20 = ORIWRdK %r21r20, 64175, implicit-def %sreg
+ $r21r20 = ORIWRdK $r21r20, 64175, implicit-def $sreg
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/ORWRdRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/ORWRdRr.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/ORWRdRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/ORWRdRr.mir Thu Feb 8 01:17:11 2018
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_orwrdrr
- ; CHECK: %r14 = ORRdRr %r14, %r20, implicit-def dead %sreg
- ; CHECK-NEXT: %r15 = ORRdRr %r15, %r21, implicit-def %sreg
+ ; CHECK: $r14 = ORRdRr $r14, $r20, implicit-def dead $sreg
+ ; CHECK-NEXT: $r15 = ORRdRr $r15, $r21, implicit-def $sreg
- %r15r14 = ORWRdRr %r15r14, %r21r20, implicit-def %sreg
+ $r15r14 = ORWRdRr $r15r14, $r21r20, implicit-def $sreg
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/OUTWARr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/OUTWARr.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/OUTWARr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/OUTWARr.mir Thu Feb 8 01:17:11 2018
@@ -15,8 +15,8 @@ body: |
; CHECK-LABEL: test
- ; CHECK: OUTARr 32, %r15
- ; CHECK-NEXT: OUTARr 31, %r14
+ ; CHECK: OUTARr 32, $r15
+ ; CHECK-NEXT: OUTARr 31, $r14
- OUTWARr 31, %r15r14
+ OUTWARr 31, $r15r14
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/POPWRd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/POPWRd.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/POPWRd.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/POPWRd.mir Thu Feb 8 01:17:11 2018
@@ -15,8 +15,8 @@ body: |
; CHECK-LABEL: test
- ; CHECK: %r29 = POPRd implicit-def %sp, implicit %sp
- ; CHECK-LABEL: %r28 = POPRd implicit-def %sp, implicit %sp
+ ; CHECK: $r29 = POPRd implicit-def $sp, implicit $sp
+ ; CHECK-LABEL: $r28 = POPRd implicit-def $sp, implicit $sp
- %r29r28 = POPWRd implicit-def %sp, implicit %sp
+ $r29r28 = POPWRd implicit-def $sp, implicit $sp
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/PUSHWRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/PUSHWRr.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/PUSHWRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/PUSHWRr.mir Thu Feb 8 01:17:11 2018
@@ -15,8 +15,8 @@ body: |
; CHECK-LABEL: test
- ; CHECK: PUSHRr %r28, implicit-def %sp, implicit %sp
- ; CHECK-NEXT: PUSHRr %r29, implicit-def %sp, implicit %sp
+ ; CHECK: PUSHRr $r28, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: PUSHRr $r29, implicit-def $sp, implicit $sp
- PUSHWRr %r29r28, implicit-def %sp, implicit %sp
+ PUSHWRr $r29r28, implicit-def $sp, implicit $sp
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/SBCIWRdK.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/SBCIWRdK.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/SBCIWRdK.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/SBCIWRdK.mir Thu Feb 8 01:17:11 2018
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_sbciwrdk
- ; CHECK: %r20 = SBCIRdK %r20, 175, implicit-def %sreg, implicit killed %sreg
- ; CHECK-NEXT: %r21 = SBCIRdK %r21, 250, implicit-def %sreg, implicit killed %sreg
+ ; CHECK: $r20 = SBCIRdK $r20, 175, implicit-def $sreg, implicit killed $sreg
+ ; CHECK-NEXT: $r21 = SBCIRdK $r21, 250, implicit-def $sreg, implicit killed $sreg
- %r21r20 = SBCIWRdK %r21r20, 64175, implicit-def %sreg, implicit %sreg
+ $r21r20 = SBCIWRdK $r21r20, 64175, implicit-def $sreg, implicit $sreg
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/SBCWRdRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/SBCWRdRr.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/SBCWRdRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/SBCWRdRr.mir Thu Feb 8 01:17:11 2018
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_sbcwrdrr
- ; CHECK: %r14 = SBCRdRr %r14, %r20, implicit-def %sreg
- ; CHECK-NEXT: %r15 = SBCRdRr %r15, %r21, implicit-def %sreg, implicit killed %sreg
+ ; CHECK: $r14 = SBCRdRr $r14, $r20, implicit-def $sreg
+ ; CHECK-NEXT: $r15 = SBCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
- %r15r14 = SBCWRdRr %r15r14, %r21r20, implicit-def %sreg, implicit %sreg
+ $r15r14 = SBCWRdRr $r15r14, $r21r20, implicit-def $sreg, implicit $sreg
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/SEXT.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/SEXT.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/SEXT.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/SEXT.mir Thu Feb 8 01:17:11 2018
@@ -15,10 +15,10 @@ body: |
; CHECK-LABEL: test
- ; CHECK: %r14 = MOVRdRr %r31
- ; CHECK-NEXT: %r15 = MOVRdRr %r31
- ; CHECK-NEXT: %r15 = LSLRd killed %r15, implicit-def %sreg
- ; CHECK-NEXT: %r15 = SBCRdRr killed %r15, killed %r15, implicit-def %sreg, implicit killed %sreg
+ ; CHECK: $r14 = MOVRdRr $r31
+ ; CHECK-NEXT: $r15 = MOVRdRr $r31
+ ; CHECK-NEXT: $r15 = LSLRd killed $r15, implicit-def $sreg
+ ; CHECK-NEXT: $r15 = SBCRdRr killed $r15, killed $r15, implicit-def $sreg, implicit killed $sreg
- %r15r14 = SEXT %r31, implicit-def %sreg
+ $r15r14 = SEXT $r31, implicit-def $sreg
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/STDWPtrQRr.mir Thu Feb 8 01:17:11 2018
@@ -15,8 +15,8 @@ body: |
; CHECK-LABEL: test
- ; CHECK: STDPtrQRr %r29r28, 10, %r0
- ; CHECK-NEXT: STDPtrQRr %r29r28, 11, %r1
+ ; CHECK: STDPtrQRr $r29r28, 10, $r0
+ ; CHECK-NEXT: STDPtrQRr $r29r28, 11, $r1
- STDWPtrQRr %r29r28, 10, %r1r0
+ STDWPtrQRr $r29r28, 10, $r1r0
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/STSWKRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/STSWKRr.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/STSWKRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/STSWKRr.mir Thu Feb 8 01:17:11 2018
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_stswkrr
- ; CHECK: STSKRr 2560, %r31
- ; CHECK-NEXT: STSKRr 2559, %r30
+ ; CHECK: STSKRr 2560, $r31
+ ; CHECK-NEXT: STSKRr 2559, $r30
- STSWKRr 2559, %r31r30
+ STSWKRr 2559, $r31r30
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPdRr.mir Thu Feb 8 01:17:11 2018
@@ -15,8 +15,8 @@ body: |
; CHECK-LABEL: test
- ; CHECK: early-clobber %r31r30 = STPtrPdRr killed %r31r30, %r29, 52
- ; CHECK-NEXT: early-clobber %r31r30 = STPtrPdRr killed %r31r30, %r28, 52
+ ; CHECK: early-clobber $r31r30 = STPtrPdRr killed $r31r30, $r29, 52
+ ; CHECK-NEXT: early-clobber $r31r30 = STPtrPdRr killed $r31r30, $r28, 52
- %r31r30 = STWPtrPdRr %r31r30, %r29r28, 52
+ $r31r30 = STWPtrPdRr $r31r30, $r29r28, 52
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrPiRr.mir Thu Feb 8 01:17:11 2018
@@ -15,8 +15,8 @@ body: |
; CHECK-LABEL: test
- ; CHECK: early-clobber %r31r30 = STPtrPiRr killed %r31r30, %r28, 52
- ; CHECK-NEXT: early-clobber %r31r30 = STPtrPiRr killed %r31r30, %r29, 52
+ ; CHECK: early-clobber $r31r30 = STPtrPiRr killed $r31r30, $r28, 52
+ ; CHECK-NEXT: early-clobber $r31r30 = STPtrPiRr killed $r31r30, $r29, 52
- %r31r30 = STWPtrPiRr %r31r30, %r29r28, 52
+ $r31r30 = STWPtrPiRr $r31r30, $r29r28, 52
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrRr.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/STWPtrRr.mir Thu Feb 8 01:17:11 2018
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_stwptrrr
- ; CHECK: STPtrRr %r31r30, %r16
- ; CHECK-NEXT: STDPtrQRr %r31r30, 1, %r17
+ ; CHECK: STPtrRr $r31r30, $r16
+ ; CHECK-NEXT: STDPtrQRr $r31r30, 1, $r17
- STWPtrRr %r31r30, %r17r16
+ STWPtrRr $r31r30, $r17r16
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/SUBIWRdK.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/SUBIWRdK.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/SUBIWRdK.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/SUBIWRdK.mir Thu Feb 8 01:17:11 2018
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_subiwrdrr
- ; CHECK: %r20 = SUBIRdK %r20, 175, implicit-def %sreg
- ; CHECK-NEXT: %r21 = SBCIRdK %r21, 250, implicit-def %sreg, implicit killed %sreg
+ ; CHECK: $r20 = SUBIRdK $r20, 175, implicit-def $sreg
+ ; CHECK-NEXT: $r21 = SBCIRdK $r21, 250, implicit-def $sreg, implicit killed $sreg
- %r21r20 = SUBIWRdK %r21r20, 64175, implicit-def %sreg
+ $r21r20 = SUBIWRdK $r21r20, 64175, implicit-def $sreg
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/SUBWRdRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/SUBWRdRr.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/SUBWRdRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/SUBWRdRr.mir Thu Feb 8 01:17:11 2018
@@ -17,8 +17,8 @@ body: |
; CHECK-LABEL: test_subwrdrr
- ; CHECK: %r14 = SUBRdRr %r14, %r20, implicit-def %sreg
- ; CHECK-NEXT: %r15 = SBCRdRr %r15, %r21, implicit-def %sreg, implicit killed %sreg
+ ; CHECK: $r14 = SUBRdRr $r14, $r20, implicit-def $sreg
+ ; CHECK-NEXT: $r15 = SBCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
- %r15r14 = SUBWRdRr %r15r14, %r21r20, implicit-def %sreg
+ $r15r14 = SUBWRdRr $r15r14, $r21r20, implicit-def $sreg
...
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/ZEXT.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/ZEXT.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/ZEXT.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/ZEXT.mir Thu Feb 8 01:17:11 2018
@@ -15,10 +15,10 @@ body: |
; CHECK-LABEL: test
- ; CHECK: %r14 = MOVRdRr %r31
- ; CHECK-NEXT: %r15 = MOVRdRr %r31
- ; CHECK-NEXT: %r15 = LSLRd killed %r15, implicit-def %sreg
- ; CHECK-NEXT: %r15 = SBCRdRr killed %r15, killed %r15, implicit-def %sreg, implicit killed %sreg
+ ; CHECK: $r14 = MOVRdRr $r31
+ ; CHECK-NEXT: $r15 = MOVRdRr $r31
+ ; CHECK-NEXT: $r15 = LSLRd killed $r15, implicit-def $sreg
+ ; CHECK-NEXT: $r15 = SBCRdRr killed $r15, killed $r15, implicit-def $sreg, implicit killed $sreg
- %r15r14 = SEXT %r31, implicit-def %sreg
+ $r15r14 = SEXT $r31, implicit-def $sreg
...
Modified: llvm/trunk/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/relax-mem/STDWPtrQRr.mir Thu Feb 8 01:17:11 2018
@@ -16,16 +16,16 @@ body: |
; CHECK-LABEL: test
; We shouldn't expand things which already have 6-bit imms.
- ; CHECK: STDWPtrQRr %r29r28, 63, %r1r0
- STDWPtrQRr %r29r28, 63, %r1r0
+ ; CHECK: STDWPtrQRr $r29r28, 63, $r1r0
+ STDWPtrQRr $r29r28, 63, $r1r0
; We shouldn't expand things which already have 6-bit imms.
- ; CHECK-NEXT: STDWPtrQRr %r29r28, 0, %r1r0
- STDWPtrQRr %r29r28, 0, %r1r0
+ ; CHECK-NEXT: STDWPtrQRr $r29r28, 0, $r1r0
+ STDWPtrQRr $r29r28, 0, $r1r0
- ; CHECK-NEXT: PUSHWRr %r29r28, implicit-def %sp, implicit %sp
- ; CHECK-NEXT: %r29r28 = SBCIWRdK %r29r28, -64, implicit-def %sreg, implicit %sreg
- ; CHECK-NEXT: STWPtrRr %r29r28, %r1r0
- ; CHECK-NEXT: POPWRd %r29r28, implicit-def %sp, implicit %sp
- STDWPtrQRr %r29r28, 64, %r1r0
+ ; CHECK-NEXT: PUSHWRr $r29r28, implicit-def $sp, implicit $sp
+ ; CHECK-NEXT: $r29r28 = SBCIWRdK $r29r28, -64, implicit-def $sreg, implicit $sreg
+ ; CHECK-NEXT: STWPtrRr $r29r28, $r1r0
+ ; CHECK-NEXT: POPWRd $r29r28, implicit-def $sp, implicit $sp
+ STDWPtrQRr $r29r28, 64, $r1r0
...
Modified: llvm/trunk/test/CodeGen/AVR/select-must-add-unconditional-jump.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/select-must-add-unconditional-jump.ll?rev=324583&r1=324582&r2=324583&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/select-must-add-unconditional-jump.ll (original)
+++ llvm/trunk/test/CodeGen/AVR/select-must-add-unconditional-jump.ll Thu Feb 8 01:17:11 2018
@@ -49,10 +49,10 @@ dead:
; basic block containing `select` needs to contain explicit jumps to
; both successors.
-; CHECK: %bb.2.finish:
+; CHECK: bb.2.finish:
; CHECK: BREQk [[BRANCHED:%bb.[0-9]+]]
; CHECK: RJMPk [[DIRECT:%bb.[0-9]+]]
; CHECK: Successors according to CFG
; CHECK-SAME-DAG: {{.*}}[[BRANCHED]]
; CHECK-SAME-DAG: {{.*}}[[DIRECT]]
-; CHECK: %bb.3.dead:
+; CHECK: bb.3.dead:
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