[PATCH] D43020: [AArch64] Don't materialize 0 with "fmov h0, .." when FullFP16 is not supported.

Sjoerd Meijer via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Feb 7 07:01:05 PST 2018


SjoerdMeijer created this revision.
SjoerdMeijer added reviewers: olista01, samparker, evandro, az.
Herald added subscribers: kristof.beyls, javed.absar, rengolin, aemerson.

We were generating:

  fmov h0, wzr

instructions when FullFP16 is not enabled.

I've not added any tests, because the problem was visible in:

  test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll

which I had to change: I don't think Cyclone has FullFP16 enabled
by default, so it shouldn't be using this v8.2a instruction.


https://reviews.llvm.org/D43020

Files:
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AArch64/AArch64InstrInfo.td
  test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll


Index: test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll
===================================================================
--- test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll
+++ test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll
@@ -16,11 +16,11 @@
 entry:
 ; ALL-LABEL: t1:
 ; ALL-NOT: fmov
-; CYCLONE: fmov h0, wzr
+; CYCLONE: ldr h0,{{.*}}
 ; CYCLONE: fmov s1, wzr
 ; CYCLONE: fmov d2, xzr
 ; CYCLONE: movi.16b v3, #0
-; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
+; OTHERS: ldr h0,{{.*}}
 ; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
 ; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
 ; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
Index: lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- lib/Target/AArch64/AArch64InstrInfo.td
+++ lib/Target/AArch64/AArch64InstrInfo.td
@@ -2717,7 +2717,7 @@
 // Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable
 let isReMaterializable = 1, isCodeGenOnly = 1, isAsCheapAsAMove = 1 in {
 def FMOVH0 : Pseudo<(outs FPR16:$Rd), (ins), [(set f16:$Rd, (fpimm0))]>,
-    Sched<[WriteF]>;
+    Sched<[WriteF]>, Requires<[HasFullFP16]>;
 def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>,
     Sched<[WriteF]>;
 def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>,
Index: lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- lib/Target/AArch64/AArch64ISelLowering.cpp
+++ lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -4924,7 +4924,8 @@
 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
   // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
   // FIXME: We should be able to handle f128 as well with a clever lowering.
-  if (Imm.isPosZero() && (VT == MVT::f16 || VT == MVT::f64 || VT == MVT::f32)) {
+  if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32 ||
+                          (VT == MVT::f16 && Subtarget->hasFullFP16()))) {
     DEBUG(dbgs() << "Legal fp imm: materialize 0 using the zero register\n");
     return true;
   }


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D43020.133211.patch
Type: text/x-patch
Size: 2117 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180207/3e3fc412/attachment.bin>


More information about the llvm-commits mailing list