[PATCH] D42885: [AMDGPU] intrintrics for byte/short load/store

[Tim Renouf via Phabricator via llvm-commits]

tpr added a comment.

If we define an overloaded intrinsic with a return type of i8, and the IR using it wants the value zero extended to i32, the frontend would then have to emit a separate zext. I guess we could optimize that to the zero-extending instruction in instruction selection, but wouldn't it be better to have the intrinsic match what the ISA instruction does by returning the zero extended i32?


Repository:
  rL LLVM

https://reviews.llvm.org/D42885