[PATCH] D42973: [ARM] FP16 mov imm pattern
Sjoerd Meijer via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 7 00:40:42 PST 2018
This revision was not accepted when it landed; it landed in state "Needs Review".
This revision was automatically updated to reflect the committed changes.
Closed by commit rL324456: [ARM] FP16 mov imm pattern (authored by SjoerdMeijer, committed by ).
Changed prior to commit:
https://reviews.llvm.org/D42973?vs=133022&id=133163#toc
Repository:
rL LLVM
https://reviews.llvm.org/D42973
Files:
llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll
Index: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
@@ -44,7 +44,7 @@
}], SDNodeXForm<fpimm, [{
APFloat InVal = N->getValueAPF();
uint32_t enc = ARM_AM::getFP16Imm(InVal);
- return CurDAG->getTargetConstant(enc, MVT::i32);
+ return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
}]>> {
let PrintMethod = "printFPImmOperand";
let ParserMatchClass = FPImmOperand;
@@ -2343,10 +2343,11 @@
let Inst{3-0} = imm{3-0};
}
-def FCONSTH : VFPAI<(outs SPR:$Sd), (ins vfp_f16imm:$imm),
+def FCONSTH : VFPAI<(outs HPR:$Sd), (ins vfp_f16imm:$imm),
VFPMiscFrm, IIC_fpUNA16,
"vmov", ".f16\t$Sd, $imm",
- []>, Requires<[HasFullFP16]> {
+ [(set HPR:$Sd, vfp_f16imm:$imm)]>,
+ Requires<[HasFullFP16]> {
bits<5> Sd;
bits<8> imm;
Index: llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll
===================================================================
--- llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll
+++ llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll
@@ -471,7 +471,20 @@
; TODO: fix immediates.
; 21. VMOV (between general-purpose register and half-precision register)
+
; 22. VMOV (immediate)
+define i32 @movi(i32 %a.coerce) {
+entry:
+ %tmp.0.extract.trunc = trunc i32 %a.coerce to i16
+ %0 = bitcast i16 %tmp.0.extract.trunc to half
+ %add = fadd half %0, 0xHC000
+ %1 = bitcast half %add to i16
+ %tmp2.0.insert.ext = zext i16 %1 to i32
+ ret i32 %tmp2.0.insert.ext
+
+; CHECK-LABEL: movi:
+; CHECK-HARDFP-FULLFP16: vmov.f16 s0, #-2.000000e+00
+}
; 23. VMUL
define float @Mul(float %a.coerce, float %b.coerce) {
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D42973.133163.patch
Type: text/x-patch
Size: 1846 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180207/53f6144e/attachment.bin>
More information about the llvm-commits
mailing list