[PATCH] D42951: [CGP] Strength reduce cmp (xor (a, -1), xor(b, -1)) => cmp (b, a)

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a reviewer: efriedma.
spatel added a comment.

I'm skeptical about trying to solve a register pressure / allocation problem this early in the pipeline (although I know it's easier to match in IR).

If we do justify this somehow, then it must be limited by TTI hooks. Breaking min/max patterns for targets that support those ops would cause regressions. For example, if we fix the matchers to see vector 'not' ops on AArch64, we'll go from:

          mvn	v0.16b, v0.16b
  	mvn	v2.16b, v2.16b
  	mvn	v1.16b, v1.16b
  	umin	v3.4s, v0.4s, v2.4s
  	umin	v3.4s, v3.4s, v1.4s
  	sub	v0.4s, v0.4s, v3.4s
  	sub	v1.4s, v1.4s, v3.4s
  	sub	v2.4s, v2.4s, v3.4s
  	bl	vuse4

To:

          mvn	v4.16b, v0.16b
  	mvn	v5.16b, v2.16b
  	cmhi	v0.4s, v0.4s, v2.4s
  	mvn	v1.16b, v1.16b
  	bsl	v0.16b, v4.16b, v5.16b
  	umin	v3.4s, v0.4s, v1.4s
  	sub	v0.4s, v4.4s, v3.4s
  	sub	v1.4s, v1.4s, v3.4s
  	sub	v2.4s, v5.4s, v3.4s
  	bl	vuse4

We'd get a similar regression on x86. That failure would show up in tests/CodeGen/AArch64/minmax-of-minmax.ll, but the pattern matching in this patch is artificially limited to scalars, so that's why we don't see it currently.


https://reviews.llvm.org/D42951