[PATCH] D42967: [ARM] Fix PR36249: add expansion rule for VLD1d64 pseudo with reg WB

[Thomas Preud'homme via Phabricator via llvm-commits]

thopre created this revision.
thopre added reviewers: rengolin, t.p.northover.
Herald added subscribers: llvm-commits, kristof.beyls, javed.absar, aemerson.

VLD1d64TPseudoWB_register and VLD1d64QPseudoWB_register are missing rules to expand them to non pseudo MIR. These are selected for ARMISD::VLD3_UPD/VLD4_UPD with v1i64 vectors in SelectVLD. This patch adds the necessary mapping to VLD1d64Twb_register and VLD1d64Qwb_register respectively. As for the _fixed variant, the cost of these is bumped for unaligned access.


Repository:
  rL LLVM

https://reviews.llvm.org/D42967

Files:
  lib/Target/ARM/ARMBaseInstrInfo.cpp
  lib/Target/ARM/ARMExpandPseudoInsts.cpp
  test/CodeGen/ARM/pr36249.mir

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