[PATCH] D42896: [SelectionDAG] Add initial implementation of TargetLowering::SimplifyDemandedVectorElts

[Simon Dardis via Phabricator via llvm-commits]

sdardis added inline comments.


================
Comment at: lib/CodeGen/SelectionDAG/TargetLowering.cpp:1303
+  APInt DemandedElts = DemandedEltMask;
+  int NumElts = DemandedElts.getBitWidth();
+  assert(VT.isVector() && "Expected vector op");
----------------
Nit: getBitWidth() returns an unsigned int, leading to a sign compare warning in the assert below.


================
Comment at: lib/CodeGen/SelectionDAG/TargetLowering.cpp:1331
+  SDLoc DL(Op);
+  int EltSizeInBits = VT.getScalarSizeInBits();
+
----------------
Nit: getScalarSizeInBits returns an unsigned int causing a -Wsign-compare warning at line 1365.


================
Comment at: test/CodeGen/Mips/cconv/vector.ll:53
 ; MIPS32R5EB:       # %bb.0:
-; MIPS32R5EB-NEXT:    addiu $sp, $sp, -16
-; MIPS32R5EB-NEXT:    .cfi_def_cfa_offset 16
-; MIPS32R5EB-NEXT:    sw $5, 8($sp)
-; MIPS32R5EB-NEXT:    sw $4, 12($sp)
-; MIPS32R5EB-NEXT:    ldi.b $w0, 0
-; MIPS32R5EB-NEXT:    lbu $1, 9($sp)
-; MIPS32R5EB-NEXT:    lbu $2, 8($sp)
-; MIPS32R5EB-NEXT:    move.v $w1, $w0
-; MIPS32R5EB-NEXT:    insert.w $w1[0], $2
-; MIPS32R5EB-NEXT:    insert.w $w1[1], $1
-; MIPS32R5EB-NEXT:    lbu $1, 12($sp)
-; MIPS32R5EB-NEXT:    insert.w $w0[0], $1
-; MIPS32R5EB-NEXT:    lbu $1, 10($sp)
-; MIPS32R5EB-NEXT:    lbu $2, 13($sp)
-; MIPS32R5EB-NEXT:    insert.w $w0[1], $2
-; MIPS32R5EB-NEXT:    insert.w $w1[2], $1
-; MIPS32R5EB-NEXT:    lbu $1, 11($sp)
-; MIPS32R5EB-NEXT:    insert.w $w1[3], $1
-; MIPS32R5EB-NEXT:    ilvr.w $w1, $w1, $w1
-; MIPS32R5EB-NEXT:    lbu $1, 14($sp)
-; MIPS32R5EB-NEXT:    shf.w $w1, $w1, 177
-; MIPS32R5EB-NEXT:    insert.w $w0[2], $1
-; MIPS32R5EB-NEXT:    lbu $1, 15($sp)
-; MIPS32R5EB-NEXT:    insert.w $w0[3], $1
+; MIPS32R5EB-NEXT:    addiu $sp, $sp, -48
+; MIPS32R5EB-NEXT:    .cfi_def_cfa_offset 48
----------------
These MIPS changes come about about the MIPS backend doesn't perform custom lowering of BUILD_VECTOR nodes which have undef elements. (See lib/Target/Mips/MipsSEISelLowering.cpp:2377)

As a result that node undergoes the normal expansion which places the elements on the stack aligned to the size of the vector register. However, MIPS's O32 ABI only provides a stack alignment of 8 rather than 16. This causes dynamic stack realignment.

A quick modification in the MIPS backend to isConstantOfUndef and lowerBUILD_VECTOR to lift that restriction shows a more reasonable code sequence with this patch. I have yet to perform further testing of this.


Repository:
  rL LLVM

https://reviews.llvm.org/D42896