[llvm] r324325 - [AArch64] Fix spelling of ICH_ELRSR_EL2 system register

[Oliver Stannard via llvm-commits]

Author: olista01
Date: Tue Feb  6 01:39:04 2018
New Revision: 324325

URL: http://llvm.org/viewvc/llvm-project?rev=324325&view=rev
Log:
[AArch64] Fix spelling of ICH_ELRSR_EL2 system register

This register was mis-spelled as ICH_ELSR_EL2, but has the correct encoding for
ICH_ELRSR_EL2.


Modified:
    llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td
    llvm/trunk/test/MC/AArch64/gicv3-regs.s
    llvm/trunk/test/MC/Disassembler/AArch64/gicv3-regs.txt

Modified: llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td?rev=324325&r1=324324&r2=324325&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td Tue Feb  6 01:39:04 2018
@@ -451,7 +451,7 @@ def : ROSysReg<"ICC_HPPIR0_EL1",     0b1
 def : ROSysReg<"ICC_RPR_EL1",        0b11, 0b000, 0b1100, 0b1011, 0b011>;
 def : ROSysReg<"ICH_VTR_EL2",        0b11, 0b100, 0b1100, 0b1011, 0b001>;
 def : ROSysReg<"ICH_EISR_EL2",       0b11, 0b100, 0b1100, 0b1011, 0b011>;
-def : ROSysReg<"ICH_ELSR_EL2",       0b11, 0b100, 0b1100, 0b1011, 0b101>;
+def : ROSysReg<"ICH_ELRSR_EL2",      0b11, 0b100, 0b1100, 0b1011, 0b101>;
 
 // v8.1a "Limited Ordering Regions" extension-specific system register
 //                         Op0    Op1     CRn     CRm    Op2

Modified: llvm/trunk/test/MC/AArch64/gicv3-regs.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/gicv3-regs.s?rev=324325&r1=324324&r2=324325&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/gicv3-regs.s (original)
+++ llvm/trunk/test/MC/AArch64/gicv3-regs.s Tue Feb  6 01:39:04 2018
@@ -7,7 +7,7 @@
         mrs x29, icc_rpr_el1
         mrs x4, ich_vtr_el2
         mrs x24, ich_eisr_el2
-        mrs x9, ich_elsr_el2
+        mrs x9, ich_elrsr_el2
         mrs x24, icc_bpr1_el1
         mrs x14, icc_bpr0_el1
         mrs x19, icc_pmr_el1
@@ -63,7 +63,7 @@
 // CHECK: mrs      x29, {{icc_rpr_el1|ICC_RPR_EL1}}           // encoding: [0x7d,0xcb,0x38,0xd5]
 // CHECK: mrs      x4, {{ich_vtr_el2|ICH_VTR_EL2}}            // encoding: [0x24,0xcb,0x3c,0xd5]
 // CHECK: mrs      x24, {{ich_eisr_el2|ICH_EISR_EL2}}          // encoding: [0x78,0xcb,0x3c,0xd5]
-// CHECK: mrs      x9, {{ich_elsr_el2|ICH_ELSR_EL2}}           // encoding: [0xa9,0xcb,0x3c,0xd5]
+// CHECK: mrs      x9, {{ich_elrsr_el2|ICH_ELRSR_EL2}}           // encoding: [0xa9,0xcb,0x3c,0xd5]
 // CHECK: mrs      x24, {{icc_bpr1_el1|ICC_BPR1_EL1}}          // encoding: [0x78,0xcc,0x38,0xd5]
 // CHECK: mrs      x14, {{icc_bpr0_el1|ICC_BPR0_EL1}}          // encoding: [0x6e,0xc8,0x38,0xd5]
 // CHECK: mrs      x19, {{icc_pmr_el1|ICC_PMR_EL1}}           // encoding: [0x13,0x46,0x38,0xd5]

Modified: llvm/trunk/test/MC/Disassembler/AArch64/gicv3-regs.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/gicv3-regs.txt?rev=324325&r1=324324&r2=324325&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/gicv3-regs.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AArch64/gicv3-regs.txt Tue Feb  6 01:39:04 2018
@@ -16,7 +16,7 @@
 0x78 0xcb 0x3c 0xd5
 # CHECK: mrs      x24, {{ich_eisr_el2|ICH_EISR_EL2}}
 0xa9 0xcb 0x3c 0xd5
-# CHECK: mrs      x9, {{ich_elsr_el2|ICH_ELSR_EL2}}
+# CHECK: mrs      x9, {{ich_elrsr_el2|ICH_ELRSR_EL2}}
 0x78 0xcc 0x38 0xd5
 # CHECK: mrs      x24, {{icc_bpr1_el1|ICC_BPR1_EL1}}
 0x6e 0xc8 0x38 0xd5