[llvm] r324002 - [DAGCombiner] When folding (insert_subvector undef, (bitcast (extract_subvector N1, Idx)), Idx) -> (bitcast N1) make sure that N1 has the same total size as the original output

Hans Wennborg via llvm-commits llvm-commits at lists.llvm.org
Mon Feb 5 01:33:54 PST 2018


Merged to 6.0 in r324216.

On Thu, Feb 1, 2018 at 9:48 PM, Craig Topper via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Author: ctopper
> Date: Thu Feb  1 12:48:50 2018
> New Revision: 324002
>
> URL: http://llvm.org/viewvc/llvm-project?rev=324002&view=rev
> Log:
> [DAGCombiner] When folding (insert_subvector undef, (bitcast (extract_subvector N1, Idx)), Idx) -> (bitcast N1) make sure that N1 has the same total size as the original output
>
> We were only checking the element count, but not the total width. This could cause illegal bitcasts to be created if for example the output was 512-bits, but N1 is 256 bits, and the extraction size was 128-bits.
>
> Fixes PR36199
>
> Differential Revision: https://reviews.llvm.org/D42809
>
> Added:
>     llvm/trunk/test/CodeGen/X86/pr36199.ll
> Modified:
>     llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=324002&r1=324001&r2=324002&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Feb  1 12:48:50 2018
> @@ -16465,7 +16465,9 @@ SDValue DAGCombiner::visitINSERT_SUBVECT
>        N1.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR &&
>        N1.getOperand(0).getOperand(1) == N2 &&
>        N1.getOperand(0).getOperand(0).getValueType().getVectorNumElements() ==
> -          VT.getVectorNumElements()) {
> +          VT.getVectorNumElements() &&
> +      N1.getOperand(0).getOperand(0).getValueType().getSizeInBits() ==
> +          VT.getSizeInBits()) {
>      return DAG.getBitcast(VT, N1.getOperand(0).getOperand(0));
>    }
>
>
> Added: llvm/trunk/test/CodeGen/X86/pr36199.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr36199.ll?rev=324002&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/pr36199.ll (added)
> +++ llvm/trunk/test/CodeGen/X86/pr36199.ll Thu Feb  1 12:48:50 2018
> @@ -0,0 +1,22 @@
> +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
> +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skylake-avx512 | FileCheck %s
> +
> +define void @foo() unnamed_addr #0 {
> +; CHECK-LABEL: foo:
> +; CHECK:       # %bb.0:
> +; CHECK-NEXT:    vaddps %zmm0, %zmm0, %zmm0
> +; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
> +; CHECK-NEXT:    vinsertf64x4 $1, %ymm0, %zmm0, %zmm0
> +; CHECK-NEXT:    vmovups %zmm0, (%rax)
> +; CHECK-NEXT:    vzeroupper
> +; CHECK-NEXT:    retq
> +  %1 = fadd <16 x float> undef, undef
> +  %bc256 = bitcast <16 x float> %1 to <4 x i128>
> +  %2 = extractelement <4 x i128> %bc256, i32 0
> +  %3 = bitcast i128 %2 to <4 x float>
> +  %4 = shufflevector <4 x float> %3, <4 x float> undef, <16 x i32> <i32 0, i32
> +1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0,
> +i32 1, i32 2, i32 3>
> +  store <16 x float> %4, <16 x float>* undef, align 4
> +  ret void
> +}
>
>
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