[llvm] r324060 - [SystemZ] Update test case (NFC)

[Jonas Paulsson via llvm-commits]

Author: jonpa
Date: Thu Feb  1 23:52:02 2018
New Revision: 324060

URL: http://llvm.org/viewvc/llvm-project?rev=324060&view=rev
Log:
[SystemZ]  Update test case (NFC)

test/CodeGen/SystemZ/vec-trunc-to-i1.ll was marked as a temporary
FAIL when it was previously updated when it needed one more COPY.
This was however wrong, since the loop body had been reduced
significantly, and it was actually an improvement.

Review: Ulrich Weigand.

Modified:
    llvm/trunk/test/CodeGen/SystemZ/vec-trunc-to-i1.ll

Modified: llvm/trunk/test/CodeGen/SystemZ/vec-trunc-to-i1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/vec-trunc-to-i1.ll?rev=324060&r1=324059&r2=324060&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/vec-trunc-to-i1.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/vec-trunc-to-i1.ll Thu Feb  1 23:52:02 2018
@@ -2,7 +2,6 @@
 ;
 ; Check that a widening truncate to a vector of i1 elements can be handled.
 
-; NOTE: REG2 is actually not needed (tempororary FAIL)
 define void @pr32275(<4 x i8> %B15) {
 ; CHECK-LABEL: pr32275:
 ; CHECK:       # %bb.0: # %BB
@@ -11,9 +10,10 @@ define void @pr32275(<4 x i8> %B15) {
 ; CHECK-NEXT:    vlgvb %r1, %v24, 1
 ; CHECK-NEXT:    vlvgp [[REG1:%v[0-9]]], %r1, %r0
 ; CHECK-NEXT:    vlgvb %r0, %v24, 0
+; CHECK-NEXT:    vlgvb [[REG3:%r[0-9]]], %v24, 2
+; CHECK:       .LBB0_1:
 ; CHECK-DAG:     vlr [[REG2:%v[0-9]]], [[REG1]]
 ; CHECK-DAG:     vlvgf [[REG2]], %r0, 0
-; CHECK-DAG:     vlgvb [[REG3:%r[0-9]]], %v24, 2
 ; CHECK-NEXT:    vlvgf [[REG2]], [[REG3]], 2
 ; CHECK-NEXT:    vn [[REG2]], [[REG2]], [[REG0]]
 ; CHECK-NEXT:    vlgvf [[REG4:%r[0-9]]], [[REG2]], 3