[PATCH] D42675: [RISCV] Define getSetCCResultType for setting vector setCC type

[Phabricator via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL324054: [RISCV] Define getSetCCResultType for setting vector setCC type (authored by shiva, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D42675?vs=132092&id=132529#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D42675

Files:
  llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h
  llvm/trunk/test/CodeGen/RISCV/get-setcc-result-type.ll


Index: llvm/trunk/test/CodeGen/RISCV/get-setcc-result-type.ll
===================================================================
--- llvm/trunk/test/CodeGen/RISCV/get-setcc-result-type.ll
+++ llvm/trunk/test/CodeGen/RISCV/get-setcc-result-type.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32I %s
+
+define void @getSetCCResultType(<4 x i32>* %p, <4 x i32>* %q) {
+; RV32I-LABEL: getSetCCResultType:
+; RV32I:       # %bb.0: # %entry
+; RV32I-NEXT:    lw a1, 12(a0)
+; RV32I-NEXT:    xor a1, a1, zero
+; RV32I-NEXT:    seqz a1, a1
+; RV32I-NEXT:    neg a1, a1
+; RV32I-NEXT:    sw a1, 12(a0)
+; RV32I-NEXT:    lw a1, 8(a0)
+; RV32I-NEXT:    xor a1, a1, zero
+; RV32I-NEXT:    seqz a1, a1
+; RV32I-NEXT:    neg a1, a1
+; RV32I-NEXT:    sw a1, 8(a0)
+; RV32I-NEXT:    lw a1, 4(a0)
+; RV32I-NEXT:    xor a1, a1, zero
+; RV32I-NEXT:    seqz a1, a1
+; RV32I-NEXT:    neg a1, a1
+; RV32I-NEXT:    sw a1, 4(a0)
+; RV32I-NEXT:    lw a1, 0(a0)
+; RV32I-NEXT:    xor a1, a1, zero
+; RV32I-NEXT:    seqz a1, a1
+; RV32I-NEXT:    neg a1, a1
+; RV32I-NEXT:    sw a1, 0(a0)
+; RV32I-NEXT:    ret
+entry:
+  %0 = load <4 x i32>, <4 x i32>* %p, align 16
+  %cmp = icmp eq <4 x i32> %0, zeroinitializer
+  %sext = sext <4 x i1> %cmp to <4 x i32>
+  store <4 x i32> %sext, <4 x i32>* %p, align 16
+  ret void
+}
Index: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -116,6 +116,13 @@
   setMinimumJumpTableEntries(INT_MAX);
 }
 
+EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
+                                            EVT VT) const {
+  if (!VT.isVector())
+    return getPointerTy(DL);
+  return VT.changeVectorElementTypeToInteger();
+}
+
 // Changes the condition code and swaps operands if necessary, so the SetCC
 // operation matches one of the comparisons supported directly in the RISC-V
 // ISA.
Index: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h
===================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h
+++ llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h
@@ -51,6 +51,9 @@
   EmitInstrWithCustomInserter(MachineInstr &MI,
                               MachineBasicBlock *BB) const override;
 
+  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
+                         EVT VT) const override;
+
 private:
   void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
                         const SmallVectorImpl<ISD::InputArg> &Ins,


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D42675.132529.patch
Type: text/x-patch
Size: 2786 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180202/b27951d3/attachment.bin>