[llvm] r324054 - [RISCV] Define getSetCCResultType for setting vector setCC type

[Shiva Chen via llvm-commits]

Author: shiva
Date: Thu Feb  1 18:43:18 2018
New Revision: 324054

URL: http://llvm.org/viewvc/llvm-project?rev=324054&view=rev
Log:
[RISCV] Define getSetCCResultType for setting vector setCC type

To avoid trigger "No default SetCC type for vectors!" Assertion

Differential Revision: https://reviews.llvm.org/D42675

Added:
    llvm/trunk/test/CodeGen/RISCV/get-setcc-result-type.ll
Modified:
    llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h

Modified: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp?rev=324054&r1=324053&r2=324054&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp Thu Feb  1 18:43:18 2018
@@ -116,6 +116,13 @@ RISCVTargetLowering::RISCVTargetLowering
   setMinimumJumpTableEntries(INT_MAX);
 }
 
+EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
+                                            EVT VT) const {
+  if (!VT.isVector())
+    return getPointerTy(DL);
+  return VT.changeVectorElementTypeToInteger();
+}
+
 // Changes the condition code and swaps operands if necessary, so the SetCC
 // operation matches one of the comparisons supported directly in the RISC-V
 // ISA.

Modified: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h?rev=324054&r1=324053&r2=324054&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h Thu Feb  1 18:43:18 2018
@@ -51,6 +51,9 @@ public:
   EmitInstrWithCustomInserter(MachineInstr &MI,
                               MachineBasicBlock *BB) const override;
 
+  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
+                         EVT VT) const override;
+
 private:
   void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
                         const SmallVectorImpl<ISD::InputArg> &Ins,

Added: llvm/trunk/test/CodeGen/RISCV/get-setcc-result-type.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/get-setcc-result-type.ll?rev=324054&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/get-setcc-result-type.ll (added)
+++ llvm/trunk/test/CodeGen/RISCV/get-setcc-result-type.ll Thu Feb  1 18:43:18 2018
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32I %s
+
+define void @getSetCCResultType(<4 x i32>* %p, <4 x i32>* %q) {
+; RV32I-LABEL: getSetCCResultType:
+; RV32I:       # %bb.0: # %entry
+; RV32I-NEXT:    lw a1, 12(a0)
+; RV32I-NEXT:    xor a1, a1, zero
+; RV32I-NEXT:    seqz a1, a1
+; RV32I-NEXT:    neg a1, a1
+; RV32I-NEXT:    sw a1, 12(a0)
+; RV32I-NEXT:    lw a1, 8(a0)
+; RV32I-NEXT:    xor a1, a1, zero
+; RV32I-NEXT:    seqz a1, a1
+; RV32I-NEXT:    neg a1, a1
+; RV32I-NEXT:    sw a1, 8(a0)
+; RV32I-NEXT:    lw a1, 4(a0)
+; RV32I-NEXT:    xor a1, a1, zero
+; RV32I-NEXT:    seqz a1, a1
+; RV32I-NEXT:    neg a1, a1
+; RV32I-NEXT:    sw a1, 4(a0)
+; RV32I-NEXT:    lw a1, 0(a0)
+; RV32I-NEXT:    xor a1, a1, zero
+; RV32I-NEXT:    seqz a1, a1
+; RV32I-NEXT:    neg a1, a1
+; RV32I-NEXT:    sw a1, 0(a0)
+; RV32I-NEXT:    ret
+entry:
+  %0 = load <4 x i32>, <4 x i32>* %p, align 16
+  %cmp = icmp eq <4 x i32> %0, zeroinitializer
+  %sext = sext <4 x i1> %cmp to <4 x i32>
+  store <4 x i32> %sext, <4 x i32>* %p, align 16
+  ret void
+}