[PATCH] D40855: [PowerPC] LSR tunings for PowerPC

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp updated this revision to Diff 132449.
stefanp added a comment.

Modified the tuning formula to take into consideration the idea that we shouldn’t be enlarging the class of equal items.
After looking into the LSR algorithm we discovered that if we enlarge the space of equal items we do not favor unchanged code as we had initially desired.
Therefore, this change does almost exactly what the default `isLSRCostLess` function does (from the base class) except that number of instructions has been added as the most important category to compare.


https://reviews.llvm.org/D40855

Files:
  lib/Target/PowerPC/PPCTargetTransformInfo.cpp
  lib/Target/PowerPC/PPCTargetTransformInfo.h
  test/Transforms/LoopStrengthReduce/PowerPC/lsr-insns-3.ll


Index: test/Transforms/LoopStrengthReduce/PowerPC/lsr-insns-3.ll
===================================================================
--- /dev/null
+++ test/Transforms/LoopStrengthReduce/PowerPC/lsr-insns-3.ll
@@ -0,0 +1,57 @@
+; RUN: llc < %s -O2 -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
+
+; LLC checks that LSR prefers less instructions to less induction variables
+; Without the PPC specific LSR cost model, extra addition instructions
+; will occur within the loop before the call to _ZN6myTypeC1Ev.
+
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-unknown-linux-gnu"
+
+%struct.myType2 = type <{ i32, i8, %struct.myType, [2 x i8] }>
+%struct.myType = type { i8 }
+
+define nonnull %struct.myType2* @_Z6myIniti(i64 signext %n) local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+; CHECK-LABEL: _Z6myIniti:
+; CHECK:  [[LABEL1:.LBB[0-9A-Z_]+]]:
+; CHECK:    mr {{[0-9]+}}, [[REG1:[0-9]+]]
+; CHECK-NEXT:    bl _ZN6myTypeC1Ev
+; CHECK:    addi [[REG2:[0-9]+]], [[REG2]], -8
+; CHECK-NEXT:    addi [[REG1]], [[REG1]], 8
+; CHECK-NEXT:    cmpldi [[REG2]], 0
+; CHECK-NEXT:    bne 0, [[LABEL1]]
+
+entry:
+  %call = tail call i8* @_Znam(i64 %n) #5
+  %cast = bitcast i8* %call to %struct.myType2*
+  %arrayctor.end = getelementptr inbounds %struct.myType2, %struct.myType2* %cast, i64 %n
+  br label %arrayctor.loop
+
+arrayctor.loop:                                   ; preds = %invoke.cont, %new.ctorloop
+  %arrayctor.cur = phi %struct.myType2* [ %cast, %entry ], [ %arrayctor.next, %invoke.cont ]
+  %x.i = getelementptr inbounds %struct.myType2, %struct.myType2* %arrayctor.cur, i64 0, i32 2
+  invoke void @_ZN6myTypeC1Ev(%struct.myType* nonnull %x.i)
+          to label %invoke.cont unwind label %lpad
+
+invoke.cont:                                      ; preds = %arrayctor.loop
+  %arrayctor.next = getelementptr inbounds %struct.myType2, %struct.myType2* %arrayctor.cur, i64 1
+  %arrayctor.done = icmp eq %struct.myType2* %arrayctor.next, %arrayctor.end
+  br i1 %arrayctor.done, label %arrayctor.cont, label %arrayctor.loop
+
+arrayctor.cont:                                   ; preds = %invoke.cont, %entry
+  ret %struct.myType2* %cast
+
+lpad:                                             ; preds = %arrayctor.loop
+  %landing = landingpad { i8*, i32 }
+          cleanup
+  tail call void @_ZdaPv(i8* nonnull %call) #6
+  resume { i8*, i32 } %landing
+}
+
+declare noalias nonnull i8* @_Znam(i64) local_unnamed_addr #2
+
+declare i32 @__gxx_personality_v0(...)
+
+declare void @_ZdaPv(i8*) local_unnamed_addr #3
+
+declare void @_ZN6myTypeC1Ev(%struct.myType*) unnamed_addr #4
+
Index: lib/Target/PowerPC/PPCTargetTransformInfo.h
===================================================================
--- lib/Target/PowerPC/PPCTargetTransformInfo.h
+++ lib/Target/PowerPC/PPCTargetTransformInfo.h
@@ -57,6 +57,9 @@
   void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
                                TTI::UnrollingPreferences &UP);
 
+  bool isLSRCostLess(TargetTransformInfo::LSRCost &C1,
+                     TargetTransformInfo::LSRCost &C2);
+
   /// @}
 
   /// \name Vector TTI Implementations
Index: lib/Target/PowerPC/PPCTargetTransformInfo.cpp
===================================================================
--- lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -256,6 +256,19 @@
   return true;
 }
 
+bool PPCTTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1,
+                               TargetTransformInfo::LSRCost &C2) {
+  // This is mainly the default cost calculation. The only difference
+  //  is that now the number of instructions is the most important
+  //  metric.
+  return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost,
+                  C1.NumIVMuls, C1.NumBaseAdds,
+                  C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
+         std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost,
+                  C2.NumIVMuls, C2.NumBaseAdds,
+                  C2.ScaleCost, C2.ImmCost, C2.SetupCost);
+}
+
 unsigned PPCTTIImpl::getNumberOfRegisters(bool Vector) {
   if (Vector && !ST->hasAltivec() && !ST->hasQPX())
     return 0;


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D40855.132449.patch
Type: text/x-patch
Size: 4214 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180201/c28667b5/attachment.bin>