[PATCH] D41949: [RISCV] [WIP] implement li pseudo instruction

[Ana Pazos via Phabricator via llvm-commits]

apazos added inline comments.


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Comment at: lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:601
   case Match_Success:
-    Inst.setLoc(IDLoc);
-    Out.EmitInstruction(Inst, getSTI());
-    return false;
+    return processInstruction(Inst, IDLoc, Out, STI);
   case Match_MissingFeature:
----------------
You changed getSTI() -> STI, was it intentional?


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Comment at: lib/Target/RISCV/MCTargetDesc/RISCVMCPseudoExpansion.cpp:34
+        *STI);
+  } else if (Hi20) {
+    Out.EmitInstruction(MCInstBuilder(RISCV::LUI).addReg(DestReg).addImm(Hi20),
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extra {}


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Comment at: lib/Target/RISCV/MCTargetDesc/RISCVMCPseudoExpansion.cpp:38
+  } else {
+    Out.EmitInstruction(MCInstBuilder(RISCV::ADDI)
+                            .addReg(DestReg)
----------------
extra {}


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Comment at: lib/Target/RISCV/RISCVAsmPrinter.cpp:74
+    const MachineOperand &ImmOp = MI->getOperand(1);
+    emitRISCVLoadImm(DstRegOp.getReg(), ImmOp.getImm(), *OutStreamer,
+                     &getSubtargetInfo());
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can't we return the new instruction from this function and reuse the EmitToStreamer call below.  This way we reduce the places to insert compression calls, when instruction compression at MC level is enabled.


https://reviews.llvm.org/D41949