[PATCH] D42784: [ARM] Allow Half types in ConstantPool

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer created this revision.
SjoerdMeijer added reviewers: t.p.northover, olista01, john.brawn.
Herald added subscribers: kristof.beyls, javed.absar, aemerson.

Hi @t.p.northover,
I'm adding FP16 support, and have test cases that try to load half float
literals from a constant pool, but ConstantIslands is running in this assert:

  Size >= 4 && "Too small constant pool entry"

So I've simply changed this assert and added VLDRH to load f16 literals.
This seems to do very sensible things, but while I am familiarising myself
with ConstantIslands, I was wondering if you know off top of your
head how many assumptions I am breaking that Size should be >= 4 :)
Cheers,
Sjoerd.


https://reviews.llvm.org/D42784

Files:
  lib/Target/ARM/ARMConstantIslandPass.cpp
  test/CodeGen/ARM/fp16-instructions.ll


Index: test/CodeGen/ARM/fp16-instructions.ll
===================================================================
--- test/CodeGen/ARM/fp16-instructions.ll
+++ test/CodeGen/ARM/fp16-instructions.ll
@@ -1,15 +1,15 @@
 ; SOFT:
-; RUN: llc < %s -mtriple=arm-none-eabi -float-abi=soft     | FileCheck %s --check-prefix=CHECK-SOFT
+; RUN: llc < %s -mtriple=arm-none-eabi -float-abi=soft     | FileCheck %s --check-prefixes=CHECK,CHECK-SOFT
 
 ; SOFTFP:
-; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+vfp3        | FileCheck %s --check-prefix=CHECK-SOFTFP-VFP3
-; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+vfp4        | FileCheck %s --check-prefix=CHECK-SOFTFP-FP16
-; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+fullfp16    | FileCheck %s --check-prefix=CHECK-SOFTFP-FULLFP16
+; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+vfp3        | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-VFP3
+; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+vfp4        | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-FP16
+; RUN: llc < %s -mtriple=arm-none-eabi -mattr=+fullfp16    | FileCheck %s --check-prefixes=CHECK,CHECK-SOFTFP-FULLFP16
 
 ; HARD:
-; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+vfp3      | FileCheck %s --check-prefix=CHECK-HARDFP-VFP3
-; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+vfp4      | FileCheck %s --check-prefix=CHECK-HARDFP-FP16
-; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+fullfp16  | FileCheck %s --check-prefix=CHECK-HARDFP-FULLFP16
+; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+vfp3      | FileCheck %s --check-prefixes=CHECK,CHECK-HARDFP-VFP3
+; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+vfp4      | FileCheck %s --check-prefixes=CHECK,CHECK-HARDFP-FP16
+; RUN: llc < %s -mtriple=arm-none-eabihf -mattr=+fullfp16  | FileCheck %s --check-prefixes=CHECK,CHECK-HARDFP-FULLFP16
 
 define float @Add(float %a.coerce, float %b.coerce) local_unnamed_addr {
 entry:
@@ -25,6 +25,8 @@
   %5 = bitcast i32 %tmp4.0.insert.ext to float
   ret float %5
 
+; CHECK-LABEL: Add:
+
 ; CHECK-SOFT:  bl  __aeabi_h2f
 ; CHECK-SOFT:  bl  __aeabi_h2f
 ; CHECK-SOFT:  bl  __aeabi_fadd
@@ -64,5 +66,23 @@
 
 ; CHECK-HARDFP-FULLFP16:       vadd.f16  s0, s0, s1
 ; CHECK-HARDFP-FULLFP16-NEXT:  mov pc, lr
+}
 
+define float @AddImm(float %A.coerce) local_unnamed_addr {
+entry:
+  %0 = bitcast float %A.coerce to i32
+  %tmp.0.extract.trunc = trunc i32 %0 to i16
+  %1 = bitcast i16 %tmp.0.extract.trunc to half
+  %add = fadd half %1, 0xH3CF0
+  %2 = bitcast half %add to i16
+  %tmp2.0.insert.ext = zext i16 %2 to i32
+  %3 = bitcast i32 %tmp2.0.insert.ext to float
+  ret float %3
+
+; CHECK-LABEL: AddImm:
+
+; CHECK-HARDFP-FULLFP16:       vldr.16 [[S2:s[0-9]]], .LCPI{{.*}}
+; CHECK-HARDFP-FULLFP16-NEXT:  vadd.f16  s0, s0, [[S2]]
+; CHECK-HARDFP-FULLFP16-NEXT:  mov pc, lr
 }
+
Index: lib/Target/ARM/ARMConstantIslandPass.cpp
===================================================================
--- lib/Target/ARM/ARMConstantIslandPass.cpp
+++ lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -510,7 +510,7 @@
   const DataLayout &TD = MF->getDataLayout();
   for (unsigned i = 0, e = CPs.size(); i != e; ++i) {
     unsigned Size = TD.getTypeAllocSize(CPs[i].getType());
-    assert(Size >= 4 && "Too small constant pool entry");
+    assert(Size >= 2 && "Too small constant pool entry");
     unsigned Align = CPs[i].getAlignment();
     assert(isPowerOf2_32(Align) && "Invalid alignment");
     // Verify that all constant pool entries are a multiple of their alignment.
@@ -820,6 +820,11 @@
             Scale = 4;  // +-(offset_8*4)
             NegOk = true;
             break;
+          case ARM::VLDRH:
+            Bits = 8;
+            Scale = 2;  // +-(offset_8*2)
+            NegOk = true;
+            break;
 
           case ARM::tLDRHi:
             Bits = 5;


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