[llvm] r323869 - [ARM] Lower lower saturate to 0 and lower saturate to -1 using bit-operations
Evgenii Stepanov via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 31 15:00:09 PST 2018
Reverted in 323929.
See https://reviews.llvm.org/D42574 for the explanation.
On Wed, Jan 31, 2018 at 5:20 AM, Pablo Barrio via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Author: pabbar01
> Date: Wed Jan 31 05:20:10 2018
> New Revision: 323869
>
> URL: http://llvm.org/viewvc/llvm-project?rev=323869&view=rev
> Log:
> [ARM] Lower lower saturate to 0 and lower saturate to -1 using bit-operations
>
> Summary:
> Expressions of the form x < 0 ? 0 : x; and x < -1 ? -1 : x can be lowered using bit-operations instead of branching or conditional moves
>
> In thumb-mode this results in a two-instruction sequence, a shift followed by a bic or or while in ARM/thumb2 mode that has flexible second operand the shift can be folded into a single bic/or instructions. In most cases this results in smaller code and possibly less branches, and in no case larger than before.
>
> Patch by Marten Svanfeldt.
>
> Reviewers: fhahn, pbarrio
>
> Reviewed By: pbarrio
>
> Subscribers: efriedma, rogfer01, aemerson, javed.absar, kristof.beyls, llvm-commits
>
> Differential Revision: https://reviews.llvm.org/D42574
>
> Added:
> llvm/trunk/test/CodeGen/ARM/sat-to-bitop.ll
> Modified:
> llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> llvm/trunk/test/CodeGen/ARM/atomic-op.ll
> llvm/trunk/test/CodeGen/ARM/select.ll
> llvm/trunk/test/CodeGen/Thumb/select.ll
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=323869&r1=323868&r2=323869&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Jan 31 05:20:10 2018
> @@ -4407,6 +4407,26 @@ SDValue ARMTargetLowering::LowerSELECT_C
> SDValue TrueVal = Op.getOperand(2);
> SDValue FalseVal = Op.getOperand(3);
>
> + // Try to convert expressions of the form x < k ? k : x (and similar forms) into
> + // more efficient bit operations, which is possible when k is 0 or -1
> + // On ARM and Thumb-2 which has flexible operand 2 this will result in single
> + // instructions. On Thumb the shift and the bit operation will be two instructions.
> + SDValue *K = isa<ConstantSDNode>(LHS) ? &LHS : isa<ConstantSDNode>(RHS)
> + ? &RHS
> + : nullptr;
> + SDValue KTmp = isa<ConstantSDNode>(TrueVal) ? TrueVal : FalseVal;
> + SDValue V = (KTmp == TrueVal) ? FalseVal : TrueVal;
> +
> + if (K && isLowerSaturate(LHS, RHS, TrueVal, FalseVal, CC, *K) && *K == KTmp) {
> + SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, V, DAG.getConstant(31, dl, VT));
> + if (isNullConstant(*K)) {
> + SDValue NotShiftV = DAG.getNode(ISD::XOR, dl, VT, ShiftV, DAG.getConstant(-1, dl, VT));
> + return DAG.getNode(ISD::AND, dl, VT, V, NotShiftV);
> + } else if (isAllOnesConstant(*K)) {
> + return DAG.getNode(ISD::OR, dl, VT, V, ShiftV);
> + }
> + }
> +
> if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
> DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
> dl);
>
> Modified: llvm/trunk/test/CodeGen/ARM/atomic-op.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-op.ll?rev=323869&r1=323868&r2=323869&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/atomic-op.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/atomic-op.ll Wed Jan 31 05:20:10 2018
> @@ -129,11 +129,12 @@ entry:
> store i32 %9, i32* %old
> call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
> ; CHECK: ldrex
> - ; CHECK: cmp
> + ; CHECK: bic
> + ; CHECK-NOT: cmp
> ; CHECK: strex
> ; CHECK-T1: bl ___sync_fetch_and_max_4
> ; CHECK-T1-M0: bl ___sync_fetch_and_max_4
> - ; CHECK-BAREMETAL: cmp
> + ; CHECK-BAREMETAL: bic
> ; CHECK-BAREMETAL-NOT: __sync
> %10 = atomicrmw max i32* %val2, i32 0 monotonic
> store i32 %10, i32* %old
>
> Added: llvm/trunk/test/CodeGen/ARM/sat-to-bitop.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/sat-to-bitop.ll?rev=323869&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/sat-to-bitop.ll (added)
> +++ llvm/trunk/test/CodeGen/ARM/sat-to-bitop.ll Wed Jan 31 05:20:10 2018
> @@ -0,0 +1,132 @@
> +; RUN: llc -mtriple=arm %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM --check-prefix=CHECK-CMP
> +; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-T --check-prefix=CHECK-CMP
> +; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-T2 --check-prefix=CHECK-CMP
> +
> +
> +; Check for clipping against 0 that should result in bic
> +;
> +; Base tests with different bit widths
> +;
> +
> +; x < 0 ? 0 : x
> +; 32-bit base test
> +define i32 @sat0_base_32bit(i32 %x) #0 {
> +; CHECK-LABEL: sat0_base_32bit:
> +; CHECK-CMP-NOT: cmp
> +; CHECK-ARM: bic {{r[0-9]}}, [[INPUT:r[0-9]]], [[INPUT]], asr #31
> +; CHECK-T2: bic.w {{r[0-9]}}, [[INPUT:r[0-9]]], [[INPUT]], asr #31
> +; CHECK-T: asrs [[IM:r[0-9]]], {{r[0-9]}}, #31
> +; CHECK-T-NEXT: bics {{r[0-9]}}, [[IM]]
> +entry:
> + %cmpLow = icmp slt i32 %x, 0
> + %saturateLow = select i1 %cmpLow, i32 0, i32 %x
> + ret i32 %saturateLow
> +}
> +
> +; x < 0 ? 0 : x
> +; 16-bit base test
> +define i16 @sat0_base_16bit(i16 %x) #0 {
> +; CHECK-LABEL: sat0_base_16bit:
> +; CHECK-CMP-NOT: cmp
> +; CHECK-ARM: bic {{r[0-9]}}, [[INPUT:r[0-9]]], [[INPUT]], asr #31
> +; CHECK-T2: bic.w {{r[0-9]}}, [[INPUT:r[0-9]]], [[INPUT]], asr #31
> +; CHECK-T: asrs [[IM:r[0-9]]], {{r[0-9]}}, #31
> +; CHECK-T-NEXT: bics {{r[0-9]}}, [[IM]]
> +entry:
> + %cmpLow = icmp slt i16 %x, 0
> + %saturateLow = select i1 %cmpLow, i16 0, i16 %x
> + ret i16 %saturateLow
> +}
> +
> +; x < 0 ? 0 : x
> +; 8-bit base test
> +define i8 @sat0_base_8bit(i8 %x) #0 {
> +; CHECK-LABEL: sat0_base_8bit:
> +; CHECK-CMP-NOT: cmp
> +; CHECK-ARM: bic {{r[0-9]}}, [[INPUT:r[0-9]]], [[INPUT]], asr #31
> +; CHECK-T2: bic.w {{r[0-9]}}, [[INPUT:r[0-9]]], [[INPUT]], asr #31
> +; CHECK-T: asrs [[IM:r[0-9]]], {{r[0-9]}}, #31
> +; CHECK-T-NEXT: bics {{r[0-9]}}, [[IM]]
> +entry:
> + %cmpLow = icmp slt i8 %x, 0
> + %saturateLow = select i1 %cmpLow, i8 0, i8 %x
> + ret i8 %saturateLow
> +}
> +
> +; Test where the conditional is formed in a different way
> +
> +; x > 0 ? x : 0
> +define i32 @sat0_lower_1(i32 %x) #0 {
> +; CHECK-LABEL: sat0_lower_1:
> +; CHECK-CMP-NOT: cmp
> +; CHECK-ARM: bic {{r[0-9]}}, [[INPUT:r[0-9]]], [[INPUT]], asr #31
> +; CHECK-T2: bic.w {{r[0-9]}}, [[INPUT:r[0-9]]], [[INPUT]], asr #31
> +; CHECK-T: asrs [[IM:r[0-9]]], {{r[0-9]}}, #31
> +; CHECK-T-NEXT: bics {{r[0-9]}}, [[IM]]
> +entry:
> + %cmpGt = icmp sgt i32 %x, 0
> + %saturateLow = select i1 %cmpGt, i32 %x, i32 0
> + ret i32 %saturateLow
> +}
> +
> +
> +; Check for clipping against -1 that should result in orr
> +;
> +; Base tests with different bit widths
> +;
> +
> +; x < -1 ? -1 : x
> +; 32-bit base test
> +define i32 @sat1_base_32bit(i32 %x) #0 {
> +; CHECK-LABEL: sat1_base_32bit:
> +; CHECK-CMP-NOT: cmp
> +; CHECK-ARM: orr {{r[0-9]}}, [[INPUT:r[0-9]]], [[INPUT]], asr #31
> +; CHECK-T2: orr.w {{r[0-9]}}, [[INPUT:r[0-9]]], [[INPUT]], asr #31
> +; CHECK-T: asrs [[IM:r[0-9]]], {{r[0-9]}}, #31
> +; CHECK-T-NEXT: orrs {{r[0-9]}}, [[IM]]
> +entry:
> + %cmpLow = icmp slt i32 %x, -1
> + %saturateLow = select i1 %cmpLow, i32 -1, i32 %x
> + ret i32 %saturateLow
> +}
> +
> +; x < -1 ? -1 : x
> +; 16-bit base test
> +; Note this currently fails due to combination of constant hoisting and bitcasts
> +define i16 @sat1_base_16bit(i16 %x) #0 {
> +; CHECK-LABEL: sat1_base_16bit:
> +entry:
> + %cmpLow = icmp slt i16 %x, -1
> + %saturateLow = select i1 %cmpLow, i16 -1, i16 %x
> + ret i16 %saturateLow
> +}
> +
> +; x < -1 ? -1 : x
> +; 8-bit base test
> +define i8 @sat1_base_8bit(i8 %x) #0 {
> +; CHECK-LABEL: sat1_base_8bit:
> +; CHECK-ARM: orr {{r[0-9]}}, [[INPUT:r[0-9]]], [[INPUT]], asr #31
> +; CHECK-ARM-NOT: cmp
> +; CHECK-T2: orr.w {{r[0-9]}}, [[INPUT:r[0-9]]], [[INPUT]], asr #31
> +; CHECK-T2-NOT: cmp
> +entry:
> + %cmpLow = icmp slt i8 %x, -1
> + %saturateLow = select i1 %cmpLow, i8 -1, i8 %x
> + ret i8 %saturateLow
> +}
> +
> +; Test where the conditional is formed in a different way
> +
> +; x > -1 ? x : -1
> +define i32 @sat1_lower_1(i32 %x) #0 {
> +; CHECK-LABEL: sat1_lower_1:
> +; CHECK-ARM: orr {{r[0-9]}}, [[INPUT:r[0-9]]], [[INPUT]], asr #31
> +; CHECK-T2: orr.w {{r[0-9]}}, [[INPUT:r[0-9]]], [[INPUT]], asr #31
> +; CHECK-T: asrs [[IM:r[0-9]]], {{r[0-9]}}, #31
> +; CHECK-T-NEXT: orrs {{r[0-9]}}, [[IM]]
> +; CHECK-CMP-NOT: cmp
> +entry:
> + %cmpGt = icmp sgt i32 %x, -1
> + %saturateLow = select i1 %cmpGt, i32 %x, i32 -1
> + ret i32 %saturateLow
> +}
>
> Modified: llvm/trunk/test/CodeGen/ARM/select.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/select.ll?rev=323869&r1=323868&r2=323869&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/select.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/select.ll Wed Jan 31 05:20:10 2018
> @@ -62,7 +62,7 @@ entry:
>
> define double @f7(double %a, double %b) {
> ;CHECK-LABEL: f7:
> -;CHECK: movlt
> +;CHECK: bic
> ;CHECK: movge
> ;CHECK-VFP-LABEL: f7:
> ;CHECK-VFP: vmovmi
>
> Modified: llvm/trunk/test/CodeGen/Thumb/select.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/select.ll?rev=323869&r1=323868&r2=323869&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Thumb/select.ll (original)
> +++ llvm/trunk/test/CodeGen/Thumb/select.ll Wed Jan 31 05:20:10 2018
> @@ -73,8 +73,8 @@ define double @f7(double %a, double %b)
> ret double %tmp1
> }
> ; CHECK-LABEL: f7:
> -; CHECK: blt
> -; CHECK: {{blt|bge}}
> +; CHECK: bge
> +; CHECK: bic
> ; CHECK: __ltdf2
> ; CHECK-EABI-LABEL: f7:
> ; CHECK-EABI: __aeabi_dcmplt
>
>
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