[llvm] r323916 - [Hexagon] Rename HexagonISelLowering::getNode to getInstr, NFC
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 31 13:17:04 PST 2018
Author: kparzysz
Date: Wed Jan 31 13:17:03 2018
New Revision: 323916
URL: http://llvm.org/viewvc/llvm-project?rev=323916&view=rev
Log:
[Hexagon] Rename HexagonISelLowering::getNode to getInstr, NFC
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
llvm/trunk/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=323916&r1=323915&r2=323916&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Wed Jan 31 13:17:03 2018
@@ -2481,16 +2481,16 @@ HexagonTargetLowering::LowerVECTOR_SHUFF
SDValue Concat10 = DAG.getNode(HexagonISD::COMBINE, dl,
typeJoin({ty(Op1), ty(Op0)}), {Op1, Op0});
if (MaskIdx == (0x06040200 | MaskUnd))
- return getNode(Hexagon::S2_vtrunehb, dl, VecTy, {Concat10}, DAG);
+ return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat10}, DAG);
if (MaskIdx == (0x07050301 | MaskUnd))
- return getNode(Hexagon::S2_vtrunohb, dl, VecTy, {Concat10}, DAG);
+ return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat10}, DAG);
SDValue Concat01 = DAG.getNode(HexagonISD::COMBINE, dl,
typeJoin({ty(Op0), ty(Op1)}), {Op0, Op1});
if (MaskIdx == (0x02000604 | MaskUnd))
- return getNode(Hexagon::S2_vtrunehb, dl, VecTy, {Concat01}, DAG);
+ return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat01}, DAG);
if (MaskIdx == (0x03010705 | MaskUnd))
- return getNode(Hexagon::S2_vtrunohb, dl, VecTy, {Concat01}, DAG);
+ return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat01}, DAG);
}
if (ByteMask.size() == 8) {
@@ -2506,23 +2506,23 @@ HexagonTargetLowering::LowerVECTOR_SHUFF
// Halfword picks.
if (MaskIdx == (0x0d0c050409080100ull | MaskUnd))
- return getNode(Hexagon::S2_shuffeh, dl, VecTy, {Op1, Op0}, DAG);
+ return getInstr(Hexagon::S2_shuffeh, dl, VecTy, {Op1, Op0}, DAG);
if (MaskIdx == (0x0f0e07060b0a0302ull | MaskUnd))
- return getNode(Hexagon::S2_shuffoh, dl, VecTy, {Op1, Op0}, DAG);
+ return getInstr(Hexagon::S2_shuffoh, dl, VecTy, {Op1, Op0}, DAG);
if (MaskIdx == (0x0d0c090805040100ull | MaskUnd))
- return getNode(Hexagon::S2_vtrunewh, dl, VecTy, {Op1, Op0}, DAG);
+ return getInstr(Hexagon::S2_vtrunewh, dl, VecTy, {Op1, Op0}, DAG);
if (MaskIdx == (0x0f0e0b0a07060302ull | MaskUnd))
- return getNode(Hexagon::S2_vtrunowh, dl, VecTy, {Op1, Op0}, DAG);
+ return getInstr(Hexagon::S2_vtrunowh, dl, VecTy, {Op1, Op0}, DAG);
if (MaskIdx == (0x0706030205040100ull | MaskUnd)) {
VectorPair P = opSplit(Op0, dl, DAG);
- return getNode(Hexagon::S2_packhl, dl, VecTy, {P.second, P.first}, DAG);
+ return getInstr(Hexagon::S2_packhl, dl, VecTy, {P.second, P.first}, DAG);
}
// Byte packs.
if (MaskIdx == (0x0e060c040a020800ull | MaskUnd))
- return getNode(Hexagon::S2_shuffeb, dl, VecTy, {Op1, Op0}, DAG);
+ return getInstr(Hexagon::S2_shuffeb, dl, VecTy, {Op1, Op0}, DAG);
if (MaskIdx == (0x0f070d050b030901ull | MaskUnd))
- return getNode(Hexagon::S2_shuffob, dl, VecTy, {Op1, Op0}, DAG);
+ return getInstr(Hexagon::S2_shuffob, dl, VecTy, {Op1, Op0}, DAG);
}
return SDValue();
@@ -2573,7 +2573,7 @@ HexagonTargetLowering::LowerBITCAST(SDVa
if (ResTy == MVT::v8i1) {
SDValue Sc = DAG.getBitcast(tyScalar(InpTy), InpV);
SDValue Ext = DAG.getZExtOrTrunc(Sc, dl, MVT::i32);
- return getNode(Hexagon::C2_tfrrp, dl, ResTy, Ext, DAG);
+ return getInstr(Hexagon::C2_tfrrp, dl, ResTy, Ext, DAG);
}
return SDValue();
@@ -2664,8 +2664,8 @@ HexagonTargetLowering::buildVector32(Arr
Consts[1]->getZExtValue() << 16;
return DAG.getBitcast(MVT::v2i16, DAG.getConstant(V, dl, MVT::i32));
}
- SDValue N = getNode(Hexagon::A2_combine_ll, dl, MVT::i32,
- {Elem[1], Elem[0]}, DAG);
+ SDValue N = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32,
+ {Elem[1], Elem[0]}, DAG);
return DAG.getBitcast(MVT::v2i16, N);
}
@@ -2710,7 +2710,7 @@ HexagonTargetLowering::buildVector32(Arr
SDValue B0 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[0], T0});
SDValue B1 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[2], T1});
- SDValue R = getNode(Hexagon::A2_combine_ll, dl, MVT::i32, {B1, B0}, DAG);
+ SDValue R = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32, {B1, B0}, DAG);
return DAG.getBitcast(MVT::v4i8, R);
}
@@ -2810,7 +2810,7 @@ HexagonTargetLowering::extractVector(SDV
// If the value extracted is a single bit, use tstbit.
if (ValWidth == 1) {
- SDValue A0 = getNode(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG);
+ SDValue A0 = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG);
return DAG.getNode(HexagonISD::TSTBIT, dl, MVT::i1, A0, IdxV);
}
@@ -2949,7 +2949,7 @@ HexagonTargetLowering::expandPredicate(S
assert(ty(Vec32).getSizeInBits() == 32);
if (isUndef(Vec32))
return DAG.getUNDEF(MVT::i64);
- return getNode(Hexagon::S2_vsxtbh, dl, MVT::i64, {Vec32}, DAG);
+ return getInstr(Hexagon::S2_vsxtbh, dl, MVT::i64, {Vec32}, DAG);
}
SDValue
@@ -2958,7 +2958,7 @@ HexagonTargetLowering::contractPredicate
assert(ty(Vec64).getSizeInBits() == 64);
if (isUndef(Vec64))
return DAG.getUNDEF(MVT::i32);
- return getNode(Hexagon::S2_vtrunehb, dl, MVT::i32, {Vec64}, DAG);
+ return getInstr(Hexagon::S2_vtrunehb, dl, MVT::i32, {Vec64}, DAG);
}
SDValue
@@ -3013,7 +3013,7 @@ HexagonTargetLowering::LowerBUILD_VECTOR
Rs[i] = DAG.getNode(ISD::OR, dl, MVT::i32, Rs[2*i], Rs[2*i+1]);
}
// Move the value directly to a predicate register.
- return getNode(Hexagon::C2_tfrrp, dl, VecTy, {Rs[0]}, DAG);
+ return getInstr(Hexagon::C2_tfrrp, dl, VecTy, {Rs[0]}, DAG);
}
return SDValue();
@@ -3248,8 +3248,8 @@ HexagonTargetLowering::ReplaceNodeResult
case ISD::BITCAST:
// Handle a bitcast from v8i1 to i8.
if (N->getValueType(0) == MVT::i8) {
- SDValue P = getNode(Hexagon::C2_tfrpr, dl, MVT::i32,
- N->getOperand(0), DAG);
+ SDValue P = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32,
+ N->getOperand(0), DAG);
Results.push_back(P);
}
break;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h?rev=323916&r1=323915&r2=323916&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.h Wed Jan 31 13:17:03 2018
@@ -316,8 +316,8 @@ namespace HexagonISD {
return Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF;
return Op.getOpcode() == ISD::UNDEF;
}
- SDValue getNode(unsigned MachineOpc, const SDLoc &dl, MVT Ty,
- ArrayRef<SDValue> Ops, SelectionDAG &DAG) const {
+ SDValue getInstr(unsigned MachineOpc, const SDLoc &dl, MVT Ty,
+ ArrayRef<SDValue> Ops, SelectionDAG &DAG) const {
SDNode *N = DAG.getMachineNode(MachineOpc, dl, Ty, Ops);
return SDValue(N, 0);
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp?rev=323916&r1=323915&r2=323916&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp Wed Jan 31 13:17:03 2018
@@ -207,8 +207,8 @@ HexagonTargetLowering::buildHvxVectorReg
// Construct two halves in parallel, then or them together.
assert(4*Words.size() == Subtarget.getVectorLength());
- SDValue HalfV0 = getNode(Hexagon::V6_vd0, dl, VecTy, {}, DAG);
- SDValue HalfV1 = getNode(Hexagon::V6_vd0, dl, VecTy, {}, DAG);
+ SDValue HalfV0 = getInstr(Hexagon::V6_vd0, dl, VecTy, {}, DAG);
+ SDValue HalfV1 = getInstr(Hexagon::V6_vd0, dl, VecTy, {}, DAG);
SDValue S = DAG.getConstant(4, dl, MVT::i32);
for (unsigned i = 0; i != NumWords/2; ++i) {
SDValue N = DAG.getNode(HexagonISD::VINSERTW0, dl, VecTy,
@@ -257,8 +257,8 @@ HexagonTargetLowering::createHvxPrefixPr
return S;
// Fill the bytes beyond BlockLen with 0s.
MVT BoolTy = MVT::getVectorVT(MVT::i1, HwLen);
- SDValue Q = getNode(Hexagon::V6_pred_scalar2, dl, BoolTy,
- {DAG.getConstant(BlockLen, dl, MVT::i32)}, DAG);
+ SDValue Q = getInstr(Hexagon::V6_pred_scalar2, dl, BoolTy,
+ {DAG.getConstant(BlockLen, dl, MVT::i32)}, DAG);
SDValue M = DAG.getNode(HexagonISD::Q2V, dl, ByteTy, Q);
return DAG.getNode(ISD::AND, dl, ByteTy, S, M);
}
@@ -404,7 +404,7 @@ HexagonTargetLowering::extractHvxElement
SDValue ExtB = extractHvxElementReg(ByteVec, IdxV, dl, MVT::i32, DAG);
SDValue Zero = DAG.getTargetConstant(0, dl, MVT::i32);
- return getNode(Hexagon::C2_cmpgtui, dl, MVT::i1, {ExtB, Zero}, DAG);
+ return getInstr(Hexagon::C2_cmpgtui, dl, MVT::i1, {ExtB, Zero}, DAG);
}
SDValue
@@ -573,8 +573,8 @@ HexagonTargetLowering::extractHvxSubvect
SDValue W1 = DAG.getNode(HexagonISD::VEXTRACTW, dl, MVT::i32,
{ShuffV, DAG.getConstant(4, dl, MVT::i32)});
SDValue Vec64 = DAG.getNode(HexagonISD::COMBINE, dl, MVT::v8i8, {W1, W0});
- return getNode(Hexagon::A4_vcmpbgtui, dl, ResTy,
- {Vec64, DAG.getTargetConstant(0, dl, MVT::i32)}, DAG);
+ return getInstr(Hexagon::A4_vcmpbgtui, dl, ResTy,
+ {Vec64, DAG.getTargetConstant(0, dl, MVT::i32)}, DAG);
}
SDValue
@@ -697,9 +697,9 @@ HexagonTargetLowering::insertHvxSubvecto
// subvector should be inserted at index 0. Generate a predicate mask
// and use vmux to do the insertion.
MVT BoolTy = MVT::getVectorVT(MVT::i1, HwLen);
- SDValue Q = getNode(Hexagon::V6_pred_scalar2, dl, BoolTy,
- {DAG.getConstant(BlockLen, dl, MVT::i32)}, DAG);
- ByteVec = getNode(Hexagon::V6_vmux, dl, ByteTy, {Q, ByteSub, ByteVec}, DAG);
+ SDValue Q = getInstr(Hexagon::V6_pred_scalar2, dl, BoolTy,
+ {DAG.getConstant(BlockLen, dl, MVT::i32)}, DAG);
+ ByteVec = getInstr(Hexagon::V6_vmux, dl, ByteTy, {Q, ByteSub, ByteVec}, DAG);
// Rotate ByteVec back, and convert to a vector predicate.
if (!IdxN || !IdxN->isNullValue()) {
SDValue HwLenV = DAG.getConstant(HwLen, dl, MVT::i32);
@@ -875,7 +875,7 @@ HexagonTargetLowering::LowerHvxMul(SDVal
MVT ExtTy = typeExtElem(ResTy, 2);
unsigned MpyOpc = ElemTy == MVT::i8 ? Hexagon::V6_vmpybv
: Hexagon::V6_vmpyhv;
- SDValue M = getNode(MpyOpc, dl, ExtTy, {Vs, Vt}, DAG);
+ SDValue M = getInstr(MpyOpc, dl, ExtTy, {Vs, Vt}, DAG);
// Discard high halves of the resulting values, collect the low halves.
for (unsigned I = 0; I < VecLen; I += 2) {
@@ -892,10 +892,10 @@ HexagonTargetLowering::LowerHvxMul(SDVal
// T1 = V6_vaslw T0, 16
// T2 = V6_vmpyiewuh_acc T1, Vs, Vt
SDValue S16 = DAG.getConstant(16, dl, MVT::i32);
- SDValue T0 = getNode(Hexagon::V6_vmpyiowh, dl, ResTy, {Vs, Vt}, DAG);
- SDValue T1 = getNode(Hexagon::V6_vaslw, dl, ResTy, {T0, S16}, DAG);
- SDValue T2 = getNode(Hexagon::V6_vmpyiewuh_acc, dl, ResTy,
- {T1, Vs, Vt}, DAG);
+ SDValue T0 = getInstr(Hexagon::V6_vmpyiowh, dl, ResTy, {Vs, Vt}, DAG);
+ SDValue T1 = getInstr(Hexagon::V6_vaslw, dl, ResTy, {T0, S16}, DAG);
+ SDValue T2 = getInstr(Hexagon::V6_vmpyiewuh_acc, dl, ResTy,
+ {T1, Vs, Vt}, DAG);
return T2;
}
default:
@@ -928,7 +928,7 @@ HexagonTargetLowering::LowerHvxMulh(SDVa
unsigned MpyOpc = ElemTy == MVT::i8
? (IsSigned ? Hexagon::V6_vmpybv : Hexagon::V6_vmpyubv)
: (IsSigned ? Hexagon::V6_vmpyhv : Hexagon::V6_vmpyuhv);
- SDValue M = getNode(MpyOpc, dl, ExtTy, {Vs, Vt}, DAG);
+ SDValue M = getInstr(MpyOpc, dl, ExtTy, {Vs, Vt}, DAG);
// Discard low halves of the resulting values, collect the high halves.
for (unsigned I = 0; I < VecLen; I += 2) {
@@ -958,15 +958,15 @@ HexagonTargetLowering::LowerHvxMulh(SDVa
// Denote Hi(Vs) = Vs':
// = [Vs'*s Hi(Vt)*2^16 + Vs' *su Lo(Vt) + V6_vmpyewuh(Vt,Vs)] >> 16
// = Vs'*s Hi(Vt) + (V6_vmpyiewuh(Vs',Vt) + V6_vmpyewuh(Vt,Vs)) >> 16
- SDValue T0 = getNode(Hexagon::V6_vmpyewuh, dl, ResTy, {Vt, Vs}, DAG);
+ SDValue T0 = getInstr(Hexagon::V6_vmpyewuh, dl, ResTy, {Vt, Vs}, DAG);
// Get Vs':
- SDValue S0 = getNode(Hexagon::V6_vasrw, dl, ResTy, {Vs, S16}, DAG);
- SDValue T1 = getNode(Hexagon::V6_vmpyiewuh_acc, dl, ResTy,
- {T0, S0, Vt}, DAG);
+ SDValue S0 = getInstr(Hexagon::V6_vasrw, dl, ResTy, {Vs, S16}, DAG);
+ SDValue T1 = getInstr(Hexagon::V6_vmpyiewuh_acc, dl, ResTy,
+ {T0, S0, Vt}, DAG);
// Shift by 16:
- SDValue S2 = getNode(Hexagon::V6_vasrw, dl, ResTy, {T1, S16}, DAG);
+ SDValue S2 = getInstr(Hexagon::V6_vasrw, dl, ResTy, {T1, S16}, DAG);
// Get Vs'*Hi(Vt):
- SDValue T2 = getNode(Hexagon::V6_vmpyiowh, dl, ResTy, {S0, Vt}, DAG);
+ SDValue T2 = getInstr(Hexagon::V6_vmpyiowh, dl, ResTy, {S0, Vt}, DAG);
// Add:
SDValue T3 = DAG.getNode(ISD::ADD, dl, ResTy, {S2, T2});
return T3;
@@ -982,29 +982,29 @@ HexagonTargetLowering::LowerHvxMulh(SDVa
};
MVT PairTy = typeJoin({ResTy, ResTy});
- SDValue P = getNode(Hexagon::V6_lvsplatw, dl, ResTy,
- {DAG.getConstant(0x02020202, dl, MVT::i32)}, DAG);
+ SDValue P = getInstr(Hexagon::V6_lvsplatw, dl, ResTy,
+ {DAG.getConstant(0x02020202, dl, MVT::i32)}, DAG);
// Multiply-unsigned halfwords:
// LoVec = Vs.uh[2i] * Vt.uh[2i],
// HiVec = Vs.uh[2i+1] * Vt.uh[2i+1]
- SDValue T0 = getNode(Hexagon::V6_vmpyuhv, dl, PairTy, {Vs, Vt}, DAG);
+ SDValue T0 = getInstr(Hexagon::V6_vmpyuhv, dl, PairTy, {Vs, Vt}, DAG);
// The low halves in the LoVec of the pair can be discarded. They are
// not added to anything (in the full-precision product), so they cannot
// produce a carry into the higher bits.
- SDValue T1 = getNode(Hexagon::V6_vlsrw, dl, ResTy, {LoVec(T0), S16}, DAG);
+ SDValue T1 = getInstr(Hexagon::V6_vlsrw, dl, ResTy, {LoVec(T0), S16}, DAG);
// Swap low and high halves in Vt, and do the halfword multiplication
// to get products Vs.uh[2i] * Vt.uh[2i+1] and Vs.uh[2i+1] * Vt.uh[2i].
- SDValue D0 = getNode(Hexagon::V6_vdelta, dl, ResTy, {Vt, P}, DAG);
- SDValue T2 = getNode(Hexagon::V6_vmpyuhv, dl, PairTy, {Vs, D0}, DAG);
+ SDValue D0 = getInstr(Hexagon::V6_vdelta, dl, ResTy, {Vt, P}, DAG);
+ SDValue T2 = getInstr(Hexagon::V6_vmpyuhv, dl, PairTy, {Vs, D0}, DAG);
// T2 has mixed products of halfwords: Lo(Vt)*Hi(Vs) and Hi(Vt)*Lo(Vs).
// These products are words, but cannot be added directly because the
// sums could overflow. Add these products, by halfwords, where each sum
// of a pair of halfwords gives a word.
- SDValue T3 = getNode(Hexagon::V6_vadduhw, dl, PairTy,
- {LoVec(T2), HiVec(T2)}, DAG);
+ SDValue T3 = getInstr(Hexagon::V6_vadduhw, dl, PairTy,
+ {LoVec(T2), HiVec(T2)}, DAG);
// Add the high halfwords from the products of the low halfwords.
SDValue T4 = DAG.getNode(ISD::ADD, dl, ResTy, {T1, LoVec(T3)});
- SDValue T5 = getNode(Hexagon::V6_vlsrw, dl, ResTy, {T4, S16}, DAG);
+ SDValue T5 = getInstr(Hexagon::V6_vlsrw, dl, ResTy, {T4, S16}, DAG);
SDValue T6 = DAG.getNode(ISD::ADD, dl, ResTy, {HiVec(T0), HiVec(T3)});
SDValue T7 = DAG.getNode(ISD::ADD, dl, ResTy, {T5, T6});
return T7;
@@ -1092,8 +1092,8 @@ HexagonTargetLowering::LowerHvxSetCC(SDV
MVT ResTy = ty(Op);
SDValue OpL = Swap ? Op.getOperand(1) : Op.getOperand(0);
SDValue OpR = Swap ? Op.getOperand(0) : Op.getOperand(1);
- SDValue CmpV = getNode(CmpOpc, dl, ResTy, {OpL, OpR}, DAG);
- return Negate ? getNode(Hexagon::V6_pred_not, dl, ResTy, {CmpV}, DAG)
+ SDValue CmpV = getInstr(CmpOpc, dl, ResTy, {OpL, OpR}, DAG);
+ return Negate ? getInstr(Hexagon::V6_pred_not, dl, ResTy, {CmpV}, DAG)
: CmpV;
}
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