[llvm] r323912 - [Hexagon] Handle ANY_EXTEND_VECTOR_INREG in lowering

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Wed Jan 31 12:48:11 2018
New Revision: 323912

URL: http://llvm.org/viewvc/llvm-project?rev=323912&view=rev
Log:
[Hexagon] Handle ANY_EXTEND_VECTOR_INREG in lowering

Added:
    llvm/trunk/test/CodeGen/Hexagon/autohvx/isel-anyext-inreg.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=323912&r1=323911&r2=323912&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Wed Jan 31 12:48:11 2018
@@ -3261,6 +3261,10 @@ HexagonTargetLowering::LowerOperation(SD
       if (Subtarget.useHVXOps())
         return LowerHvxMulh(Op, DAG);
       break;
+    case ISD::ANY_EXTEND_VECTOR_INREG:
+      if (Subtarget.useHVXOps())
+        return LowerHvxExtend(Op, DAG);
+      break;
   }
   return SDValue();
 }

Added: llvm/trunk/test/CodeGen/Hexagon/autohvx/isel-anyext-inreg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/autohvx/isel-anyext-inreg.ll?rev=323912&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/autohvx/isel-anyext-inreg.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/autohvx/isel-anyext-inreg.ll Wed Jan 31 12:48:11 2018
@@ -0,0 +1,20 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; This code causes any_extend_vector_inreg to appear in the selection DAG.
+; Make sure that it is handled instead of crashing.
+; CHECK: vmem
+
+target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
+target triple = "hexagon"
+
+define hidden fastcc void @fred() #0 {
+b0:
+  %v1 = load i16, i16* undef, align 2
+  %v2 = insertelement <16 x i16> undef, i16 %v1, i32 15
+  %v3 = zext <16 x i16> %v2 to <16 x i32>
+  %v4 = shl nuw <16 x i32> %v3, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+  store <16 x i32> %v4, <16 x i32>* undef, align 4
+  unreachable
+}
+
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }