[PATCH] D42580: [ARM] Armv8.2-A FP16 code generation (part 2/3)

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer updated this revision to Diff 132116.
SjoerdMeijer added a comment.

*) New nodes ARMISD::VMOVhr and ARMISD::VMOVrh are now defined to be clearing
the top 16 bits.

*) The match rules to instruction select vmov.f16 use the ARMISD::VMOVhr and
ARMISD nodes; thus they direct map on vmov.f16.

*) The logic in ExpandBITCAST has been simplified. Node ARMISD::VMOVhr is
created for i32->i16->f16 truncate/bitcast patterns, so this:

      t2: i32 = ..
    t7: i16 = truncate t2
  t8: f16 = bitcast t7

now becomes:

  t2: i32 = ..

t18: f16 = ARMISD::VMOVhr t2

This is what we want for soft-float ABI when half args are passed as ints. And
it is simpler than before we don't have to look at the CopyFromReg node. Thus,
we now generate this for an f16 add that works on 2 half operands that are
passed as integer args:

  vmov.f16  s0, r1
  vmov.f16  s2, r0
  vadd.f16  s0, s2, s0
  vmov.f16  r0, s0

*) For hard-float ABI and FullFP16, the initial pattern is a bit different:

        t2: f32,ch = CopyFromReg t0, Register:f32 %0
      t5: i32 = bitcast t2
    t6: i16 = truncate t5
  t7: f16 = bitcast t6

This is now a 2-step approach. First, the i32->i16->f16 truncate/bitcast
pattern matches:

      t2: f32,ch = CopyFromReg t0, Register:f32 %0
    t5: i32 = bitcast t2
  t18: f16 = ARMISD::VMOVhr t5

And then, in the 2nd step, the f32->i32 bitcast and move is rewritten to just
this:

  f16 = CopyFromReg t0, Register:f32 %1

which is what we need to avoid generating unnecessary moves for hard-float
FullFP16, and just generate the data processing instruction:

  vadd.f16  s0, s0, s1

I've kept the logic for this last rewrite also in ExpandBITCAST (as opposed to
moving it DAG combine), because I am matching the bitcast and this looks the
right place to do this.

*) Any missed bitcast rewrite opportunities will get the default legalization
treatment and result in stack stores/loads, thus these missed opportunities are
not correctness issues


https://reviews.llvm.org/D42580

Files:
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/ARMISelLowering.h
  lib/Target/ARM/ARMInstrVFP.td
  test/CodeGen/ARM/fp16-instructions.ll

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