[llvm] r323858 - [PowerPC] Return true in enableMultipleCopyHints().
Jonas Paulsson via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 31 01:26:51 PST 2018
Author: jonpa
Date: Wed Jan 31 01:26:51 2018
New Revision: 323858
URL: http://llvm.org/viewvc/llvm-project?rev=323858&view=rev
Log:
[PowerPC] Return true in enableMultipleCopyHints().
Enable multiple COPY hints to eliminate more COPYs during register allocation.
Note that this is something all targets should do, see
https://reviews.llvm.org/D38128.
Review: Nemanja Ivanovic
Modified:
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h
llvm/trunk/test/CodeGen/PowerPC/licm-tocReg.ll
llvm/trunk/test/CodeGen/PowerPC/load-two-flts.ll
llvm/trunk/test/CodeGen/PowerPC/ppc64-byval-align.ll
llvm/trunk/test/CodeGen/PowerPC/select-i1-vs-i1.ll
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h?rev=323858&r1=323857&r2=323858&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h Wed Jan 31 01:26:51 2018
@@ -85,6 +85,8 @@ public:
BitVector getReservedRegs(const MachineFunction &MF) const override;
bool isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const override;
+ bool enableMultipleCopyHints() const override { return true; }
+
/// We require the register scavenger.
bool requiresRegisterScavenging(const MachineFunction &MF) const override {
return true;
Modified: llvm/trunk/test/CodeGen/PowerPC/licm-tocReg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/licm-tocReg.ll?rev=323858&r1=323857&r2=323858&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/licm-tocReg.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/licm-tocReg.ll Wed Jan 31 01:26:51 2018
@@ -65,15 +65,15 @@
define signext i32 @test(i32 (i32)* nocapture %FP) local_unnamed_addr #0 {
; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addis 6, 2, .LC0 at toc@ha
-; CHECK-NEXT: addis 4, 2, .LC1 at toc@ha
-; CHECK-NEXT: ld 5, .LC1 at toc@l(4)
-; CHECK-NEXT: ld 6, .LC0 at toc@l(6)
-; CHECK-NEXT: lwz 4, 0(5)
-; CHECK-NEXT: lwz 7, 0(6)
-; CHECK-NEXT: cmpw 4, 7
+; CHECK-NEXT: addis 4, 2, .LC0 at toc@ha
+; CHECK-NEXT: addis 5, 2, .LC1 at toc@ha
+; CHECK-NEXT: mr 12, 3
+; CHECK-NEXT: ld 4, .LC0 at toc@l(4)
+; CHECK-NEXT: ld 5, .LC1 at toc@l(5)
+; CHECK-NEXT: lwz 6, 0(4)
; CHECK-NEXT: lwz 7, 0(5)
-; CHECK-NEXT: mr 4, 3
+; CHECK-NEXT: cmpw 6, 7
+; CHECK-NEXT: lwz 6, 0(4)
; CHECK-NEXT: bgt 0, .LBB0_2
; CHECK-NOT: addis {{[0-9]+}}, 2, .LC0 at toc@ha
; CHECK-NOT: addis {{[0-9]+}}, 2, .LC1 at toc@ha
Modified: llvm/trunk/test/CodeGen/PowerPC/load-two-flts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/load-two-flts.ll?rev=323858&r1=323857&r2=323858&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/load-two-flts.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/load-two-flts.ll Wed Jan 31 01:26:51 2018
@@ -53,8 +53,8 @@ entry:
; CHECK-NOT: ldu {{[0-9]+}}, 8(5)
; CHECK-NOT: stw
; CHECK-NOT: rldicl
-; CHECK-DAG: lfsu {{[0-9]+}}, 8(5)
-; CHECK-DAG: lfs {{[0-9]+}}, 4(5)
+; CHECK-DAG: lfsu {{[0-9]+}}, 8(3)
+; CHECK-DAG: lfs {{[0-9]+}}, 4(3)
; CHECK: blr
}
Modified: llvm/trunk/test/CodeGen/PowerPC/ppc64-byval-align.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ppc64-byval-align.ll?rev=323858&r1=323857&r2=323858&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/ppc64-byval-align.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/ppc64-byval-align.ll Wed Jan 31 01:26:51 2018
@@ -24,8 +24,7 @@ entry:
ret void
}
; CHECK-LABEL: @caller1
-; CHECK: mr [[REG:[0-9]+]], 3
-; CHECK: mr 7, [[REG]]
+; CHECK: mr 7, 3
; CHECK: bl test1
define i64 @callee2(%struct.pad* byval nocapture readnone %x, i32 signext %y, %struct.test* byval align 16 nocapture readonly %z) {
Modified: llvm/trunk/test/CodeGen/PowerPC/select-i1-vs-i1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/select-i1-vs-i1.ll?rev=323858&r1=323857&r2=323858&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/select-i1-vs-i1.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/select-i1-vs-i1.ll Wed Jan 31 01:26:51 2018
@@ -557,10 +557,8 @@ entry:
; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
-; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
-; CHECK: fmr 1, 5
+; CHECK: bclr 12, [[REG1]], 0
+; CHECK: fmr 1, 6
; CHECK: blr
}
@@ -654,10 +652,8 @@ entry:
; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
-; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
-; CHECK: fmr 1, 5
+; CHECK: bclr 12, [[REG1]], 0
+; CHECK: fmr 1, 6
; CHECK: blr
}
@@ -751,10 +747,8 @@ entry:
; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
-; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
-; CHECK: fmr 1, 5
+; CHECK: bclr 12, [[REG1]], 0
+; CHECK: fmr 1, 6
; CHECK: blr
}
@@ -848,10 +842,8 @@ entry:
; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
-; CHECK: fmr 5, 6
-; CHECK: .LBB[[BB]]:
-; CHECK: fmr 1, 5
+; CHECK: bclr 12, [[REG1]], 0
+; CHECK: fmr 1, 6
; CHECK: blr
}
@@ -1327,10 +1319,8 @@ entry:
; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
-; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
-; CHECK: qvfmr 1, 5
+; CHECK: bclr 12, [[REG1]], 0
+; CHECK: qvfmr 1, 6
; CHECK: blr
}
@@ -1424,10 +1414,8 @@ entry:
; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
-; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
-; CHECK: qvfmr 1, 5
+; CHECK: bclr 12, [[REG1]], 0
+; CHECK: qvfmr 1, 6
; CHECK: blr
}
@@ -1521,10 +1509,8 @@ entry:
; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
-; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
-; CHECK: qvfmr 1, 5
+; CHECK: bclr 12, [[REG1]], 0
+; CHECK: qvfmr 1, 6
; CHECK: blr
}
@@ -1618,10 +1604,8 @@ entry:
; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
-; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
-; CHECK: qvfmr 1, 5
+; CHECK: bclr 12, [[REG1]], 0
+; CHECK: qvfmr 1, 6
; CHECK: blr
}
@@ -1715,10 +1699,8 @@ entry:
; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
-; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
-; CHECK: qvfmr 1, 5
+; CHECK: bclr 12, [[REG1]], 0
+; CHECK: qvfmr 1, 6
; CHECK: blr
}
@@ -1812,10 +1794,8 @@ entry:
; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
-; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
-; CHECK: qvfmr 5, 6
-; CHECK: .LBB[[BB]]:
-; CHECK: qvfmr 1, 5
+; CHECK: bclr 12, [[REG1]], 0
+; CHECK: qvfmr 1, 6
; CHECK: blr
}
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