[PATCH] D42675: [RISCV] Define getSetCCResultType for setting vector setCC type

[Shiva Chen via Phabricator via llvm-commits]

shiva0217 updated this revision to Diff 132092.
shiva0217 added a comment.

Update the patch to reflect the comments.


Repository:
  rL LLVM

https://reviews.llvm.org/D42675

Files:
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  test/CodeGen/RISCV/get-setcc-result-type.ll


Index: test/CodeGen/RISCV/get-setcc-result-type.ll
===================================================================
--- /dev/null
+++ test/CodeGen/RISCV/get-setcc-result-type.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -disable-block-placement -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32I %s
+
+define void @getSetCCResultType(<4 x i32>* %p, <4 x i32>* %q) {
+; RV32I-LABEL: getSetCCResultType:
+; RV32I:       # %bb.0:
+; RV32I-NEXT: lw	a1, 12(a0)
+; RV32I-NEXT: xor	a1, a1, zero
+; RV32I-NEXT: seqz	a1, a1
+; RV32I-NEXT: neg	a1, a1
+; RV32I-NEXT: sw	a1, 12(a0)
+; RV32I-NEXT: lw	a1, 8(a0)
+; RV32I-NEXT: xor	a1, a1, zero
+; RV32I-NEXT: seqz	a1, a1
+; RV32I-NEXT: neg	a1, a1
+; RV32I-NEXT: sw	a1, 8(a0)
+; RV32I-NEXT: lw	a1, 4(a0)
+; RV32I-NEXT: xor	a1, a1, zero
+; RV32I-NEXT: seqz	a1, a1
+; RV32I-NEXT: neg	a1, a1
+; RV32I-NEXT: sw	a1, 4(a0)
+; RV32I-NEXT: lw	a1, 0(a0)
+; RV32I-NEXT: xor	a1, a1, zero
+; RV32I-NEXT: seqz	a1, a1
+; RV32I-NEXT: neg	a1, a1
+; RV32I-NEXT: sw	a1, 0(a0)
+; RV32I-NEXT: ret
+entry:
+  %0 = load <4 x i32>, <4 x i32>* %p, align 16
+  %cmp = icmp eq <4 x i32> %0, zeroinitializer
+  %sext = sext <4 x i1> %cmp to <4 x i32>
+  store <4 x i32> %sext, <4 x i32>* %p, align 16
+  ret void
+}
Index: lib/Target/RISCV/RISCVISelLowering.h
===================================================================
--- lib/Target/RISCV/RISCVISelLowering.h
+++ lib/Target/RISCV/RISCVISelLowering.h
@@ -51,6 +51,9 @@
   EmitInstrWithCustomInserter(MachineInstr &MI,
                               MachineBasicBlock *BB) const override;
 
+  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
+                         EVT VT) const override;
+
 private:
   void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
                         const SmallVectorImpl<ISD::InputArg> &Ins,
Index: lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- lib/Target/RISCV/RISCVISelLowering.cpp
+++ lib/Target/RISCV/RISCVISelLowering.cpp
@@ -116,6 +116,13 @@
   setMinimumJumpTableEntries(INT_MAX);
 }
 
+EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
+                                            EVT VT) const {
+  if (!VT.isVector())
+    return getPointerTy(DL);
+  return VT.changeVectorElementTypeToInteger();
+}
+
 // Changes the condition code and swaps operands if necessary, so the SetCC
 // operation matches one of the comparisons supported directly in the RISC-V
 // ISA.


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