[PATCH] D39386: [Power9] Allow gpr callee saved spills in prologue to vector registers rather than stack

[Zaara Syeda via Phabricator via llvm-commits]

syzaara updated this revision to Diff 132037.
syzaara added a comment.

Add handling in updateLiveness to add spilled destination register as live into all MachineBasicBlocks of the MachineFunction.


https://reviews.llvm.org/D39386

Files:
  include/llvm/CodeGen/MachineFrameInfo.h
  lib/CodeGen/PrologEpilogInserter.cpp
  lib/Target/PowerPC/PPCFrameLowering.cpp
  lib/Target/PowerPC/PPCFrameLowering.h
  test/CodeGen/PowerPC/prolog_vec_spills.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D39386.132037.patch
Type: text/x-patch
Size: 16363 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180130/68f294f1/attachment-0001.bin>